hXDP: Efficient Software Packet Processing on FPGA NICs.
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| Title: | hXDP: Efficient Software Packet Processing on FPGA NICs. |
|---|---|
| Authors: | Brunella, Marco Spaziani1 spaziani@axbryd.com, Belocchi, Giacomo1 belocchi@axbryd.com, Bonola, Marco2 salvatore@axbryd.com, Pontarelli, Salvatore3 marco@axbryd.com, Siracusano, Giuseppe4 giuseppe.siracusano@neclab.eu, Bianchi, Giuseppe5 giuseppe.bianchi@uniroma2.it, Cammarano, Aniello6 cammarano@axbryd.com, Palumbo, Alessandro5 palumbo@ing.uniroma2.it, Petrucci, Luca5 luca.petrucci@uniroma2.it, Bifulco, Roberto4 roberto.bifulco@neclab.eu |
| Source: | Communications of the ACM. Aug2022, Vol. 65 Issue 8, p91-100. 8p. 5 Diagrams, 2 Charts, 4 Graphs. |
| Subjects: | Network interface devices, Computer networks, Motherboards, Electronic data processing, Computers, Technological innovations |
| Abstract: | The network interface cards (NICs) of modern computers are changing to adapt to faster data rates and to help with the scaling issues of general-purpose CPU technologies. Among the ongoing innovations, the inclusion of programmable accelerators on the NIC's data path is particularly interesting, since it provides the opportunity to offload some of the CPU's network packet processing tasks to the accelerator. Given the strict latency constraints of packet processing tasks, accelerators are often implemented leveraging platforms such as Field-Programmable Gate Arrays (FPGAs). FPGAs can be re-programmed after deployment, to adapt to changing application requirements, and can achieve both high throughput and low latency when implementing packet processing tasks. However, they have limited resources that may need to be shared among diverse applications, and programming them is difficult and requires hardware design expertise. We present hXDP, a solution to run on FPGAs software packet processing tasks described with the eBPF technology and targeting the Linux's eXpress Data Path. hXDP uses only a fraction of the available FPGA resources, while matching the performance of high-end CPUs. The iterative execution model of eBPF is not a good fit for FPGA accelerators. Nonetheless, we show that many of the instructions of an eBPF program can be compressed, parallelized, or completely removed, when targeting a purpose-built FPGA design, thereby significantly improving performance. We implement hXDP on an FPGA NIC and evaluate it running real-world unmodified eBPF programs. Our implementation runs at 156.25MHz and uses about 15% of the FPGA resources. Despite these modest requirements, it can run dynamically loaded programs, achieves the packet processing throughput of a high-end CPU core, and provides a 10× lower packet forwarding latency. [ABSTRACT FROM AUTHOR] |
| Copyright of Communications of the ACM is the property of Association for Computing Machinery and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 158128821 AccessLevel: 6 PubType: Periodical PubTypeId: serialPeriodical PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: hXDP: Efficient Software Packet Processing on FPGA NICs. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Brunella%2C+Marco+Spaziani%22">Brunella, Marco Spaziani</searchLink><relatesTo>1</relatesTo><i> spaziani@axbryd.com</i><br /><searchLink fieldCode="AR" term="%22Belocchi%2C+Giacomo%22">Belocchi, Giacomo</searchLink><relatesTo>1</relatesTo><i> belocchi@axbryd.com</i><br /><searchLink fieldCode="AR" term="%22Bonola%2C+Marco%22">Bonola, Marco</searchLink><relatesTo>2</relatesTo><i> salvatore@axbryd.com</i><br /><searchLink fieldCode="AR" term="%22Pontarelli%2C+Salvatore%22">Pontarelli, Salvatore</searchLink><relatesTo>3</relatesTo><i> marco@axbryd.com</i><br /><searchLink fieldCode="AR" term="%22Siracusano%2C+Giuseppe%22">Siracusano, Giuseppe</searchLink><relatesTo>4</relatesTo><i> giuseppe.siracusano@neclab.eu</i><br /><searchLink fieldCode="AR" term="%22Bianchi%2C+Giuseppe%22">Bianchi, Giuseppe</searchLink><relatesTo>5</relatesTo><i> giuseppe.bianchi@uniroma2.it</i><br /><searchLink fieldCode="AR" term="%22Cammarano%2C+Aniello%22">Cammarano, Aniello</searchLink><relatesTo>6</relatesTo><i> cammarano@axbryd.com</i><br /><searchLink fieldCode="AR" term="%22Palumbo%2C+Alessandro%22">Palumbo, Alessandro</searchLink><relatesTo>5</relatesTo><i> palumbo@ing.uniroma2.it</i><br /><searchLink fieldCode="AR" term="%22Petrucci%2C+Luca%22">Petrucci, Luca</searchLink><relatesTo>5</relatesTo><i> luca.petrucci@uniroma2.it</i><br /><searchLink fieldCode="AR" term="%22Bifulco%2C+Roberto%22">Bifulco, Roberto</searchLink><relatesTo>4</relatesTo><i> roberto.bifulco@neclab.eu</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Communications+of+the+ACM%22">Communications of the ACM</searchLink>. Aug2022, Vol. 65 Issue 8, p91-100. 8p. 5 Diagrams, 2 Charts, 4 Graphs. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Network+interface+devices%22">Network interface devices</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+networks%22">Computer networks</searchLink><br /><searchLink fieldCode="DE" term="%22Motherboards%22">Motherboards</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+data+processing%22">Electronic data processing</searchLink><br /><searchLink fieldCode="DE" term="%22Computers%22">Computers</searchLink><br /><searchLink fieldCode="DE" term="%22Technological+innovations%22">Technological innovations</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: The network interface cards (NICs) of modern computers are changing to adapt to faster data rates and to help with the scaling issues of general-purpose CPU technologies. Among the ongoing innovations, the inclusion of programmable accelerators on the NIC's data path is particularly interesting, since it provides the opportunity to offload some of the CPU's network packet processing tasks to the accelerator. Given the strict latency constraints of packet processing tasks, accelerators are often implemented leveraging platforms such as Field-Programmable Gate Arrays (FPGAs). FPGAs can be re-programmed after deployment, to adapt to changing application requirements, and can achieve both high throughput and low latency when implementing packet processing tasks. However, they have limited resources that may need to be shared among diverse applications, and programming them is difficult and requires hardware design expertise. We present hXDP, a solution to run on FPGAs software packet processing tasks described with the eBPF technology and targeting the Linux's eXpress Data Path. hXDP uses only a fraction of the available FPGA resources, while matching the performance of high-end CPUs. The iterative execution model of eBPF is not a good fit for FPGA accelerators. Nonetheless, we show that many of the instructions of an eBPF program can be compressed, parallelized, or completely removed, when targeting a purpose-built FPGA design, thereby significantly improving performance. We implement hXDP on an FPGA NIC and evaluate it running real-world unmodified eBPF programs. Our implementation runs at 156.25MHz and uses about 15% of the FPGA resources. Despite these modest requirements, it can run dynamically loaded programs, achieves the packet processing throughput of a high-end CPU core, and provides a 10× lower packet forwarding latency. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Communications of the ACM is the property of Association for Computing Machinery and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1145/3543668 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 8 StartPage: 91 Subjects: – SubjectFull: Network interface devices Type: general – SubjectFull: Computer networks Type: general – SubjectFull: Motherboards Type: general – SubjectFull: Electronic data processing Type: general – SubjectFull: Computers Type: general – SubjectFull: Technological innovations Type: general Titles: – TitleFull: hXDP: Efficient Software Packet Processing on FPGA NICs. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Brunella, Marco Spaziani – PersonEntity: Name: NameFull: Belocchi, Giacomo – PersonEntity: Name: NameFull: Bonola, Marco – PersonEntity: Name: NameFull: Pontarelli, Salvatore – PersonEntity: Name: NameFull: Siracusano, Giuseppe – PersonEntity: Name: NameFull: Bianchi, Giuseppe – PersonEntity: Name: NameFull: Cammarano, Aniello – PersonEntity: Name: NameFull: Palumbo, Alessandro – PersonEntity: Name: NameFull: Petrucci, Luca – PersonEntity: Name: NameFull: Bifulco, Roberto IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 08 Text: Aug2022 Type: published Y: 2022 Identifiers: – Type: issn-print Value: 00010782 Numbering: – Type: volume Value: 65 – Type: issue Value: 8 Titles: – TitleFull: Communications of the ACM Type: main |
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