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STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse.

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Title:	STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse.
Authors:	Yue, Jinshan¹ (AUTHOR), Liu, Yongpan¹ (AUTHOR) ypliu@tsinghua.edu.cn, Yuan, Zhe¹ (AUTHOR), Feng, Xiaoyu¹ (AUTHOR), He, Yifan¹ (AUTHOR), Sun, Wenyu¹ (AUTHOR), Zhang, Zhixiao² (AUTHOR), Si, Xin² (AUTHOR), Liu, Ruhui² (AUTHOR), Wang, Zi³ (AUTHOR), Chang, Meng-Fan² (AUTHOR), Dou, Chunmeng³ (AUTHOR), Li, Xueqing¹ (AUTHOR), Liu, Ming³ (AUTHOR), Yang, Huazhong¹ (AUTHOR)
Source:	IEEE Journal of Solid-State Circuits. Aug2022, Vol. 57 Issue 8, p2560-2573. 14p.
Subjects:	Macro processors, Energy consumption, System integration, Video coding, Architectural design, Computer architecture
Abstract:	Computing-in-memory (CIM) is a promising architecture for energy-efficient neural network (NN) processors. Several CIM macros have demonstrated high energy efficiency, while CIM-based system-on-a-chip is not well explored. This work presents a CIM NN processor, named STICKER-IM, which is implemented with sophisticated system integration. Three key innovations are proposed. First, a CIM-friendly block-wise sparsity (BWS) architecture is designed, enabling both activation-sparsity-aware acceleration and weight-sparsity-aware power-saving. Second, an adaptive kernel-/channel-order (KCO) mapping and intra-/inter-macro scheduling strategy is proposed to improve macro utilization and data reuse. Third, an efficient BWS-optimized CIM (BWS-CIM) macro with adaptive power-OFF ADCs is implemented. The STICKER-IM chip was fabricated in 65-nm CMOS technology. Experimental results show 5.8–158-TOPS/W average system energy efficiency on the sparse NN models. The macro/system-level energy efficiency is $4.23\times / 3.06\times $ higher compared with the state-of-the-art CIM macros and processors. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	Computing-in-memory (CIM) is a promising architecture for energy-efficient neural network (NN) processors. Several CIM macros have demonstrated high energy efficiency, while CIM-based system-on-a-chip is not well explored. This work presents a CIM NN processor, named STICKER-IM, which is implemented with sophisticated system integration. Three key innovations are proposed. First, a CIM-friendly block-wise sparsity (BWS) architecture is designed, enabling both activation-sparsity-aware acceleration and weight-sparsity-aware power-saving. Second, an adaptive kernel-/channel-order (KCO) mapping and intra-/inter-macro scheduling strategy is proposed to improve macro utilization and data reuse. Third, an efficient BWS-optimized CIM (BWS-CIM) macro with adaptive power-OFF ADCs is implemented. The STICKER-IM chip was fabricated in 65-nm CMOS technology. Experimental results show 5.8–158-TOPS/W average system energy efficiency on the sparse NN models. The macro/system-level energy efficiency is $4.23\times / 3.06\times $ higher compared with the state-of-the-art CIM macros and processors. [ABSTRACT FROM AUTHOR]
ISSN:	00189200
DOI:	10.1109/JSSC.2022.3148273