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STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse.

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Title: STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse.
Authors: Yue, Jinshan1 (AUTHOR), Liu, Yongpan1 (AUTHOR) ypliu@tsinghua.edu.cn, Yuan, Zhe1 (AUTHOR), Feng, Xiaoyu1 (AUTHOR), He, Yifan1 (AUTHOR), Sun, Wenyu1 (AUTHOR), Zhang, Zhixiao2 (AUTHOR), Si, Xin2 (AUTHOR), Liu, Ruhui2 (AUTHOR), Wang, Zi3 (AUTHOR), Chang, Meng-Fan2 (AUTHOR), Dou, Chunmeng3 (AUTHOR), Li, Xueqing1 (AUTHOR), Liu, Ming3 (AUTHOR), Yang, Huazhong1 (AUTHOR)
Source: IEEE Journal of Solid-State Circuits. Aug2022, Vol. 57 Issue 8, p2560-2573. 14p.
Subjects: Macro processors, Energy consumption, System integration, Video coding, Architectural design, Computer architecture
Abstract: Computing-in-memory (CIM) is a promising architecture for energy-efficient neural network (NN) processors. Several CIM macros have demonstrated high energy efficiency, while CIM-based system-on-a-chip is not well explored. This work presents a CIM NN processor, named STICKER-IM, which is implemented with sophisticated system integration. Three key innovations are proposed. First, a CIM-friendly block-wise sparsity (BWS) architecture is designed, enabling both activation-sparsity-aware acceleration and weight-sparsity-aware power-saving. Second, an adaptive kernel-/channel-order (KCO) mapping and intra-/inter-macro scheduling strategy is proposed to improve macro utilization and data reuse. Third, an efficient BWS-optimized CIM (BWS-CIM) macro with adaptive power-OFF ADCs is implemented. The STICKER-IM chip was fabricated in 65-nm CMOS technology. Experimental results show 5.8–158-TOPS/W average system energy efficiency on the sparse NN models. The macro/system-level energy efficiency is $4.23\times / 3.06\times $ higher compared with the state-of-the-art CIM macros and processors. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
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Items – Name: Title
  Label: Title
  Group: Ti
  Data: STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Yue%2C+Jinshan%22">Yue, Jinshan</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Liu%2C+Yongpan%22">Liu, Yongpan</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> ypliu@tsinghua.edu.cn</i><br /><searchLink fieldCode="AR" term="%22Yuan%2C+Zhe%22">Yuan, Zhe</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Feng%2C+Xiaoyu%22">Feng, Xiaoyu</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22He%2C+Yifan%22">He, Yifan</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Sun%2C+Wenyu%22">Sun, Wenyu</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Zhang%2C+Zhixiao%22">Zhang, Zhixiao</searchLink><relatesTo>2</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Si%2C+Xin%22">Si, Xin</searchLink><relatesTo>2</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Liu%2C+Ruhui%22">Liu, Ruhui</searchLink><relatesTo>2</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Wang%2C+Zi%22">Wang, Zi</searchLink><relatesTo>3</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Chang%2C+Meng-Fan%22">Chang, Meng-Fan</searchLink><relatesTo>2</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Dou%2C+Chunmeng%22">Dou, Chunmeng</searchLink><relatesTo>3</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Li%2C+Xueqing%22">Li, Xueqing</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Liu%2C+Ming%22">Liu, Ming</searchLink><relatesTo>3</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Yang%2C+Huazhong%22">Yang, Huazhong</searchLink><relatesTo>1</relatesTo> (AUTHOR)
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22IEEE+Journal+of+Solid-State+Circuits%22">IEEE Journal of Solid-State Circuits</searchLink>. Aug2022, Vol. 57 Issue 8, p2560-2573. 14p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Macro+processors%22">Macro processors</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+consumption%22">Energy consumption</searchLink><br /><searchLink fieldCode="DE" term="%22System+integration%22">System integration</searchLink><br /><searchLink fieldCode="DE" term="%22Video+coding%22">Video coding</searchLink><br /><searchLink fieldCode="DE" term="%22Architectural+design%22">Architectural design</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+architecture%22">Computer architecture</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: Computing-in-memory (CIM) is a promising architecture for energy-efficient neural network (NN) processors. Several CIM macros have demonstrated high energy efficiency, while CIM-based system-on-a-chip is not well explored. This work presents a CIM NN processor, named STICKER-IM, which is implemented with sophisticated system integration. Three key innovations are proposed. First, a CIM-friendly block-wise sparsity (BWS) architecture is designed, enabling both activation-sparsity-aware acceleration and weight-sparsity-aware power-saving. Second, an adaptive kernel-/channel-order (KCO) mapping and intra-/inter-macro scheduling strategy is proposed to improve macro utilization and data reuse. Third, an efficient BWS-optimized CIM (BWS-CIM) macro with adaptive power-OFF ADCs is implemented. The STICKER-IM chip was fabricated in 65-nm CMOS technology. Experimental results show 5.8–158-TOPS/W average system energy efficiency on the sparse NN models. The macro/system-level energy efficiency is $4.23\times / 3.06\times $ higher compared with the state-of-the-art CIM macros and processors. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1109/JSSC.2022.3148273
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 14
        StartPage: 2560
    Subjects:
      – SubjectFull: Macro processors
        Type: general
      – SubjectFull: Energy consumption
        Type: general
      – SubjectFull: System integration
        Type: general
      – SubjectFull: Video coding
        Type: general
      – SubjectFull: Architectural design
        Type: general
      – SubjectFull: Computer architecture
        Type: general
    Titles:
      – TitleFull: STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Yue, Jinshan
      – PersonEntity:
          Name:
            NameFull: Liu, Yongpan
      – PersonEntity:
          Name:
            NameFull: Yuan, Zhe
      – PersonEntity:
          Name:
            NameFull: Feng, Xiaoyu
      – PersonEntity:
          Name:
            NameFull: He, Yifan
      – PersonEntity:
          Name:
            NameFull: Sun, Wenyu
      – PersonEntity:
          Name:
            NameFull: Zhang, Zhixiao
      – PersonEntity:
          Name:
            NameFull: Si, Xin
      – PersonEntity:
          Name:
            NameFull: Liu, Ruhui
      – PersonEntity:
          Name:
            NameFull: Wang, Zi
      – PersonEntity:
          Name:
            NameFull: Chang, Meng-Fan
      – PersonEntity:
          Name:
            NameFull: Dou, Chunmeng
      – PersonEntity:
          Name:
            NameFull: Li, Xueqing
      – PersonEntity:
          Name:
            NameFull: Liu, Ming
      – PersonEntity:
          Name:
            NameFull: Yang, Huazhong
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 08
              Text: Aug2022
              Type: published
              Y: 2022
          Identifiers:
            – Type: issn-print
              Value: 00189200
          Numbering:
            – Type: volume
              Value: 57
            – Type: issue
              Value: 8
          Titles:
            – TitleFull: IEEE Journal of Solid-State Circuits
              Type: main
ResultId 1