Compact hardware accelerator for field multipliers suitable for use in ultra-low power IoT edge devices.
Saved in:
| Title: | Compact hardware accelerator for field multipliers suitable for use in ultra-low power IoT edge devices. |
|---|---|
| Authors: | Ibrahim, Atef1,2 (AUTHOR) aa.mohamed@psau.edu.sa, Gebali, Fayez2 (AUTHOR) fayez@ece.uvic.ca |
| Source: | Alexandria Engineering Journal. Dec2022, Vol. 61 Issue 12, p13079-13087. 9p. |
| Subjects: | Array processors, Internet of things, Hardware, Finite fields, Multiplication |
| Abstract: | Adoption of IoT technology without considering its security implications may expose network systems to a variety of security breaches. In network systems, IoT edge devices are a major source of security risks. Implementing cryptographic algorithms on most IoT edge devices can be difficult due to their limited resources. As a result, compact implementations of these algorithms on these devices are required. Because the field multiplication operation is at the heart of most cryptographic algorithms, its implementation will have a significant impact on the entire cryptographic algorithm implementation. As a result, in this paper, we propose a small hardware accelerator for performing field multiplication on edge devices. The hardware accelerator is primarily composed of a processor array with a regular structure and local interconnection among its processing elements. The main advantage of the proposed hardware structure is the ability to manage its area, delay, and consumed energy by choosing the appropriate word size l. We implemented the proposed structure using ASIC technology and the obtained results attain average savings in the area of 95.9%. Also, we obtained significant average savings in energy of 63.2%. The acquired results reveal that the offered hardware accelerator is appropriate for usage in resource-constrained IoT edge devices. [ABSTRACT FROM AUTHOR] |
| Copyright of Alexandria Engineering Journal is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
|---|---|
| Header | DbId: egs DbLabel: Engineering Source An: 160910001 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
| IllustrationInfo | |
| Items | – Name: Title Label: Title Group: Ti Data: Compact hardware accelerator for field multipliers suitable for use in ultra-low power IoT edge devices. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Ibrahim%2C+Atef%22">Ibrahim, Atef</searchLink><relatesTo>1,2</relatesTo> (AUTHOR)<i> aa.mohamed@psau.edu.sa</i><br /><searchLink fieldCode="AR" term="%22Gebali%2C+Fayez%22">Gebali, Fayez</searchLink><relatesTo>2</relatesTo> (AUTHOR)<i> fayez@ece.uvic.ca</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Alexandria+Engineering+Journal%22">Alexandria Engineering Journal</searchLink>. Dec2022, Vol. 61 Issue 12, p13079-13087. 9p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Array+processors%22">Array processors</searchLink><br /><searchLink fieldCode="DE" term="%22Internet+of+things%22">Internet of things</searchLink><br /><searchLink fieldCode="DE" term="%22Hardware%22">Hardware</searchLink><br /><searchLink fieldCode="DE" term="%22Finite+fields%22">Finite fields</searchLink><br /><searchLink fieldCode="DE" term="%22Multiplication%22">Multiplication</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Adoption of IoT technology without considering its security implications may expose network systems to a variety of security breaches. In network systems, IoT edge devices are a major source of security risks. Implementing cryptographic algorithms on most IoT edge devices can be difficult due to their limited resources. As a result, compact implementations of these algorithms on these devices are required. Because the field multiplication operation is at the heart of most cryptographic algorithms, its implementation will have a significant impact on the entire cryptographic algorithm implementation. As a result, in this paper, we propose a small hardware accelerator for performing field multiplication on edge devices. The hardware accelerator is primarily composed of a processor array with a regular structure and local interconnection among its processing elements. The main advantage of the proposed hardware structure is the ability to manage its area, delay, and consumed energy by choosing the appropriate word size l. We implemented the proposed structure using ASIC technology and the obtained results attain average savings in the area of 95.9%. Also, we obtained significant average savings in energy of 63.2%. The acquired results reveal that the offered hardware accelerator is appropriate for usage in resource-constrained IoT edge devices. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Alexandria Engineering Journal is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=160910001 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1016/j.aej.2022.07.013 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 9 StartPage: 13079 Subjects: – SubjectFull: Array processors Type: general – SubjectFull: Internet of things Type: general – SubjectFull: Hardware Type: general – SubjectFull: Finite fields Type: general – SubjectFull: Multiplication Type: general Titles: – TitleFull: Compact hardware accelerator for field multipliers suitable for use in ultra-low power IoT edge devices. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Ibrahim, Atef – PersonEntity: Name: NameFull: Gebali, Fayez IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 12 Text: Dec2022 Type: published Y: 2022 Identifiers: – Type: issn-print Value: 11100168 Numbering: – Type: volume Value: 61 – Type: issue Value: 12 Titles: – TitleFull: Alexandria Engineering Journal Type: main |
| ResultId | 1 |
