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LDML: A Proposal to Reduce Leakage Power in DML Circuits.

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Title: LDML: A Proposal to Reduce Leakage Power in DML Circuits.
Authors: Yadav, Neetika1,2 (AUTHOR), Pandey, Neeta1 (AUTHOR), Nand, Deva1 (AUTHOR) devkamboj07@gmail.com
Source: Wireless Personal Communications. Mar2023, Vol. 129 Issue 2, p1009-1024. 16p.
Subjects: Leakage, NAND gates, Transistors
Abstract: This paper puts forward a proposal to reduce leakage power in dual mode logic (DML) circuits by adapting LECTOR (LEakage Control TransistOR) technique and the circuits so obtained are referred to as L-DML circuits. The concept is elucidated through footed Type A and Type B DML based gates which are called LDML-TA and LDML-TB. The leakage power for two and four input NAND and NOR gates implemented through DML and LDML circuits is measured in static and dynamic mode through simulative investigations at 90 nm and 45 nm nodes using the Symica DE tool. The performance of the proposal is investigated using standard and high threshold transistor variants in LECTOR technique. The dependence of leakage power on temperature is also studied for both DML and LDML circuits. It is observed that the leakage power of the circuits exhibits an upward trend with lowering of technology node and increase in temperature irrespective of the mode of operation. In static mode, the maximum power saving for LDML-TA is 58.9% at 27 °C whereas the corresponding saving in LDML-TB is 66.6% for 2-input design. Similarly, the LDML-TA and LDML-TB show power saving of (28.5%, 58.9%) and (32.5%, 66.6%) in (pre-charge, evaluate) states respectively in dynamic mode. [ABSTRACT FROM AUTHOR]
Copyright of Wireless Personal Communications is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: LDML: A Proposal to Reduce Leakage Power in DML Circuits.
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  Data: <searchLink fieldCode="AR" term="%22Yadav%2C+Neetika%22">Yadav, Neetika</searchLink><relatesTo>1,2</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Pandey%2C+Neeta%22">Pandey, Neeta</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Nand%2C+Deva%22">Nand, Deva</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> devkamboj07@gmail.com</i>
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  Data: <searchLink fieldCode="JN" term="%22Wireless+Personal+Communications%22">Wireless Personal Communications</searchLink>. Mar2023, Vol. 129 Issue 2, p1009-1024. 16p.
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  Data: <searchLink fieldCode="DE" term="%22Leakage%22">Leakage</searchLink><br /><searchLink fieldCode="DE" term="%22NAND+gates%22">NAND gates</searchLink><br /><searchLink fieldCode="DE" term="%22Transistors%22">Transistors</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: This paper puts forward a proposal to reduce leakage power in dual mode logic (DML) circuits by adapting LECTOR (LEakage Control TransistOR) technique and the circuits so obtained are referred to as L-DML circuits. The concept is elucidated through footed Type A and Type B DML based gates which are called LDML-TA and LDML-TB. The leakage power for two and four input NAND and NOR gates implemented through DML and LDML circuits is measured in static and dynamic mode through simulative investigations at 90 nm and 45 nm nodes using the Symica DE tool. The performance of the proposal is investigated using standard and high threshold transistor variants in LECTOR technique. The dependence of leakage power on temperature is also studied for both DML and LDML circuits. It is observed that the leakage power of the circuits exhibits an upward trend with lowering of technology node and increase in temperature irrespective of the mode of operation. In static mode, the maximum power saving for LDML-TA is 58.9% at 27 °C whereas the corresponding saving in LDML-TB is 66.6% for 2-input design. Similarly, the LDML-TA and LDML-TB show power saving of (28.5%, 58.9%) and (32.5%, 66.6%) in (pre-charge, evaluate) states respectively in dynamic mode. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Wireless Personal Communications is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1007/s11277-023-10170-4
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      – Code: eng
        Text: English
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        StartPage: 1009
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      – SubjectFull: Leakage
        Type: general
      – SubjectFull: NAND gates
        Type: general
      – SubjectFull: Transistors
        Type: general
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      – TitleFull: LDML: A Proposal to Reduce Leakage Power in DML Circuits.
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            NameFull: Yadav, Neetika
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              M: 03
              Text: Mar2023
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              Y: 2023
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