Realization of high-speed logic functions using heterojunction vertical TFET.
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| Title: | Realization of high-speed logic functions using heterojunction vertical TFET. |
|---|---|
| Authors: | Ambekar, Vikas1 (AUTHOR) vikasa.phd20.ec@nitp.ac.in, Panchore, Meena1 (AUTHOR) |
| Source: | Applied Physics A: Materials Science & Processing. Mar2023, Vol. 129 Issue 3, p1-10. 10p. 6 Diagrams, 4 Charts, 7 Graphs. |
| Subjects: | Heterojunctions, NAND gates, Logic, Indium gallium zinc oxide, Germanium, Boolean functions, Threshold voltage |
| Abstract: | In this paper, a dual-gate silicon–germanium heterojunction vertical TFET with germanium as the source material (HJ-VTFET) is proposed for realizing compact logic functions. A single device with both gate terminals is biased independently during 2D simulation to understand fundamental two-input Boolean gates (OR, NAND, AND and NOR). The vital element in attaining various logic functions using double-gate vertical TFET is deploying a gate–source connection with an appropriate choice of silicon body thickness. The OR and NAND gates are realized using n-type and p-type HJ-VTFETs, respectively, by applying an independent voltage at both gates. While the AND and NOR gates are realized using n-type and p-type HJ-VTFETs, respectively, employing the gate–source overlap method. These implementations show that an exclusive feature of TFETs, such as ambipolar conduction with tunneling dependent on gate–source overlapping, can be realized for logic functions. With such a compact implementation with HJ-VTFET, the present work revealed some serious problems, such as a large subthreshold swing (SS), a small ON-state current ( I ON ), and high propagation delay ( τ D ). For AND functionality, in contrast to pure Si-based-VTFET (Si-VTFET), the HJ-VTFET raised I ON / I OFF via 3rd-order magnitude with around 67% improvement in SS. Further, an OR gate is realized with proposed HJ-VTFET and revealed less τ D around 0.012 nS, compared to the other gates realized using HJ-VTFET. [ABSTRACT FROM AUTHOR] |
| Copyright of Applied Physics A: Materials Science & Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
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| Items | – Name: Title Label: Title Group: Ti Data: Realization of high-speed logic functions using heterojunction vertical TFET. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Ambekar%2C+Vikas%22">Ambekar, Vikas</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> vikasa.phd20.ec@nitp.ac.in</i><br /><searchLink fieldCode="AR" term="%22Panchore%2C+Meena%22">Panchore, Meena</searchLink><relatesTo>1</relatesTo> (AUTHOR) – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Applied+Physics+A%3A+Materials+Science+%26+Processing%22">Applied Physics A: Materials Science & Processing</searchLink>. Mar2023, Vol. 129 Issue 3, p1-10. 10p. 6 Diagrams, 4 Charts, 7 Graphs. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Heterojunctions%22">Heterojunctions</searchLink><br /><searchLink fieldCode="DE" term="%22NAND+gates%22">NAND gates</searchLink><br /><searchLink fieldCode="DE" term="%22Logic%22">Logic</searchLink><br /><searchLink fieldCode="DE" term="%22Indium+gallium+zinc+oxide%22">Indium gallium zinc oxide</searchLink><br /><searchLink fieldCode="DE" term="%22Germanium%22">Germanium</searchLink><br /><searchLink fieldCode="DE" term="%22Boolean+functions%22">Boolean functions</searchLink><br /><searchLink fieldCode="DE" term="%22Threshold+voltage%22">Threshold voltage</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: In this paper, a dual-gate silicon–germanium heterojunction vertical TFET with germanium as the source material (HJ-VTFET) is proposed for realizing compact logic functions. A single device with both gate terminals is biased independently during 2D simulation to understand fundamental two-input Boolean gates (OR, NAND, AND and NOR). The vital element in attaining various logic functions using double-gate vertical TFET is deploying a gate–source connection with an appropriate choice of silicon body thickness. The OR and NAND gates are realized using n-type and p-type HJ-VTFETs, respectively, by applying an independent voltage at both gates. While the AND and NOR gates are realized using n-type and p-type HJ-VTFETs, respectively, employing the gate–source overlap method. These implementations show that an exclusive feature of TFETs, such as ambipolar conduction with tunneling dependent on gate–source overlapping, can be realized for logic functions. With such a compact implementation with HJ-VTFET, the present work revealed some serious problems, such as a large subthreshold swing (SS), a small ON-state current ( I ON ), and high propagation delay ( τ D ). For AND functionality, in contrast to pure Si-based-VTFET (Si-VTFET), the HJ-VTFET raised I ON / I OFF via 3rd-order magnitude with around 67% improvement in SS. Further, an OR gate is realized with proposed HJ-VTFET and revealed less τ D around 0.012 nS, compared to the other gates realized using HJ-VTFET. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Applied Physics A: Materials Science & Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s00339-023-06419-1 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 10 StartPage: 1 Subjects: – SubjectFull: Heterojunctions Type: general – SubjectFull: NAND gates Type: general – SubjectFull: Logic Type: general – SubjectFull: Indium gallium zinc oxide Type: general – SubjectFull: Germanium Type: general – SubjectFull: Boolean functions Type: general – SubjectFull: Threshold voltage Type: general Titles: – TitleFull: Realization of high-speed logic functions using heterojunction vertical TFET. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Ambekar, Vikas – PersonEntity: Name: NameFull: Panchore, Meena IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 03 Text: Mar2023 Type: published Y: 2023 Identifiers: – Type: issn-print Value: 09478396 Numbering: – Type: volume Value: 129 – Type: issue Value: 3 Titles: – TitleFull: Applied Physics A: Materials Science & Processing Type: main |
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