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Efficient Design of FGMOS-Based Low-Power Low-Voltage XOR Gate.

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Title: Efficient Design of FGMOS-Based Low-Power Low-Voltage XOR Gate.
Authors: Sharma, Uma1 (AUTHOR) uma.16516490020@ipu.ac.in, Jhamb, Mansi1 (AUTHOR)
Source: Circuits, Systems & Signal Processing. May2023, Vol. 42 Issue 5, p2852-2871. 20p.
Subjects: Digital signal processing, NAND gates, Design techniques, Metal oxide semiconductor field-effect transistors, Low voltage systems
Abstract: Full adders (FAs) are the core elements and substantially impact the performance of digital signal processing applications such as arithmetic logic unit (ALU). In this paper, XOR gate-based FA design is presented that can operate appropriately in the domain of ultra-low voltage (LV) and low power (LP). In this treatise, FGMOS technique is used to elevate the performance in terms of design complexity and to reduce the power requirements. Important device performance characteristics such as power (pwr), delay (tp), power delay product (PDP) and energy delay product (EDP) are explored for the proposed FGMOS XOR gate design, and existing XOR designs are used to assess the results. This research paper presents a low-power FGMOS XOR gate design with a total power consumption of 5.39 pW at 0.7 V supply. Further, in this work, 1-bit FGMOS-based ALU is proposed to perform the functions of full adder, NAND, NOR and XOR. To ameliorate the performance of the circuit, FGMOS-based NAND and NOR gate designs are also proposed in this treatise. Aforementioned full adder and XOR gate along with pass-transistor logic (PTL)-based multiplexers are used to design efficient design of 1-bit ALU at 22-nm technology node. This research paper explicates the utility of FGMOS technique for the designing of high-performance complex digital circuits. [ABSTRACT FROM AUTHOR]
Copyright of Circuits, Systems & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: Efficient Design of FGMOS-Based Low-Power Low-Voltage XOR Gate.
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  Data: <searchLink fieldCode="JN" term="%22Circuits%2C+Systems+%26+Signal+Processing%22">Circuits, Systems & Signal Processing</searchLink>. May2023, Vol. 42 Issue 5, p2852-2871. 20p.
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  Data: <searchLink fieldCode="DE" term="%22Digital+signal+processing%22">Digital signal processing</searchLink><br /><searchLink fieldCode="DE" term="%22NAND+gates%22">NAND gates</searchLink><br /><searchLink fieldCode="DE" term="%22Design+techniques%22">Design techniques</searchLink><br /><searchLink fieldCode="DE" term="%22Metal+oxide+semiconductor+field-effect+transistors%22">Metal oxide semiconductor field-effect transistors</searchLink><br /><searchLink fieldCode="DE" term="%22Low+voltage+systems%22">Low voltage systems</searchLink>
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  Data: Full adders (FAs) are the core elements and substantially impact the performance of digital signal processing applications such as arithmetic logic unit (ALU). In this paper, XOR gate-based FA design is presented that can operate appropriately in the domain of ultra-low voltage (LV) and low power (LP). In this treatise, FGMOS technique is used to elevate the performance in terms of design complexity and to reduce the power requirements. Important device performance characteristics such as power (pwr), delay (tp), power delay product (PDP) and energy delay product (EDP) are explored for the proposed FGMOS XOR gate design, and existing XOR designs are used to assess the results. This research paper presents a low-power FGMOS XOR gate design with a total power consumption of 5.39 pW at 0.7 V supply. Further, in this work, 1-bit FGMOS-based ALU is proposed to perform the functions of full adder, NAND, NOR and XOR. To ameliorate the performance of the circuit, FGMOS-based NAND and NOR gate designs are also proposed in this treatise. Aforementioned full adder and XOR gate along with pass-transistor logic (PTL)-based multiplexers are used to design efficient design of 1-bit ALU at 22-nm technology node. This research paper explicates the utility of FGMOS technique for the designing of high-performance complex digital circuits. [ABSTRACT FROM AUTHOR]
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  Label:
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  Data: <i>Copyright of Circuits, Systems & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Text: English
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        Type: general
      – SubjectFull: NAND gates
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      – SubjectFull: Design techniques
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      – SubjectFull: Metal oxide semiconductor field-effect transistors
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              Text: May2023
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