Sasaki, T., Inoue, T., Omori, N., Hironaka, T., Mattausch, H. J., & Koide, T. (2005). Chip size and performance evaluations of shared cache for on-chip multiprocessor. Systems & Computers in Japan, 36(9), 1. https://doi.org/10.1002/scj.20244
Chicago Style (17th ed.) CitationSasaki, Takahiro, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans J. Mattausch, and Tetsushi Koide. "Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessor." Systems & Computers in Japan 36, no. 9 (2005): 1. https://doi.org/10.1002/scj.20244.
MLA (9th ed.) CitationSasaki, Takahiro, et al. "Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessor." Systems & Computers in Japan, vol. 36, no. 9, 2005, p. 1, https://doi.org/10.1002/scj.20244.