Chip size and performance evaluations of shared cache for on-chip multiprocessor.
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| Title: | Chip size and performance evaluations of shared cache for on-chip multiprocessor. |
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| Authors: | Sasaki, Takahiro1, Inoue, Tomohiro1, Omori, Nobuhiko2, Hironaka, Tetsuo1, Mattausch, Hans J.2, Koide, Tetsushi2 |
| Source: | Systems & Computers in Japan. 8/1/2005, Vol. 36 Issue 9, p1-13. 13p. |
| Subjects: | Multiprocessors, Multiprogramming (Electronic computers), Cache memory, Computer storage devices, Computer architecture, Computer network architectures |
| Abstract: | Recent semiconductor technology has made on-chip multiprocessors with several CPUs and cache memories on a single chip a realistic possibility. Generally, conventional multiprocessor systems with shared memory offer a simple programming model, but need a cache coherency mechanism that may become a system bottleneck. Furthermore, the same data may be cached on two or more caches, which prevents effective cache utilization. The multiport cache is one solution, but when using the conventional multiport memory architecture, the chip size of the multiport cache will increase in proportion to the square of the number of ports. On the other hand, with our proposed hierarchical multiport memory architecture, multiport memory can be implemented with a smaller chip size than by the conventional methods. This paper proposes the shared cache with a hierarchical multiport memory architecture that does not need a coherency mechanism. This paper also presents the results of performance evaluations and chip size estimations. © 2005 Wiley Periodicals, Inc. Syst Comp Jpn, 36(9): 1–13, 2005; Published online in Wiley InterScience ( |
| Copyright of Systems & Computers in Japan is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Items | – Name: Title Label: Title Group: Ti Data: Chip size and performance evaluations of shared cache for on-chip multiprocessor. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Sasaki%2C+Takahiro%22">Sasaki, Takahiro</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Inoue%2C+Tomohiro%22">Inoue, Tomohiro</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Omori%2C+Nobuhiko%22">Omori, Nobuhiko</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Hironaka%2C+Tetsuo%22">Hironaka, Tetsuo</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Mattausch%2C+Hans+J%2E%22">Mattausch, Hans J.</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Koide%2C+Tetsushi%22">Koide, Tetsushi</searchLink><relatesTo>2</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Systems+%26+Computers+in+Japan%22">Systems & Computers in Japan</searchLink>. 8/1/2005, Vol. 36 Issue 9, p1-13. 13p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Multiprocessors%22">Multiprocessors</searchLink><br /><searchLink fieldCode="DE" term="%22Multiprogramming+%28Electronic+computers%29%22">Multiprogramming (Electronic computers)</searchLink><br /><searchLink fieldCode="DE" term="%22Cache+memory%22">Cache memory</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+storage+devices%22">Computer storage devices</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+architecture%22">Computer architecture</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+network+architectures%22">Computer network architectures</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Recent semiconductor technology has made on-chip multiprocessors with several CPUs and cache memories on a single chip a realistic possibility. Generally, conventional multiprocessor systems with shared memory offer a simple programming model, but need a cache coherency mechanism that may become a system bottleneck. Furthermore, the same data may be cached on two or more caches, which prevents effective cache utilization. The multiport cache is one solution, but when using the conventional multiport memory architecture, the chip size of the multiport cache will increase in proportion to the square of the number of ports. On the other hand, with our proposed hierarchical multiport memory architecture, multiport memory can be implemented with a smaller chip size than by the conventional methods. This paper proposes the shared cache with a hierarchical multiport memory architecture that does not need a coherency mechanism. This paper also presents the results of performance evaluations and chip size estimations. © 2005 Wiley Periodicals, Inc. Syst Comp Jpn, 36(9): 1–13, 2005; Published online in Wiley InterScience (<URL>www.interscience.wiley.com</URL>). DOI 10.1002/scj.20244 [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Systems & Computers in Japan is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1002/scj.20244 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 13 StartPage: 1 Subjects: – SubjectFull: Multiprocessors Type: general – SubjectFull: Multiprogramming (Electronic computers) Type: general – SubjectFull: Cache memory Type: general – SubjectFull: Computer storage devices Type: general – SubjectFull: Computer architecture Type: general – SubjectFull: Computer network architectures Type: general Titles: – TitleFull: Chip size and performance evaluations of shared cache for on-chip multiprocessor. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Sasaki, Takahiro – PersonEntity: Name: NameFull: Inoue, Tomohiro – PersonEntity: Name: NameFull: Omori, Nobuhiko – PersonEntity: Name: NameFull: Hironaka, Tetsuo – PersonEntity: Name: NameFull: Mattausch, Hans J. – PersonEntity: Name: NameFull: Koide, Tetsushi IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 08 Text: 8/1/2005 Type: published Y: 2005 Identifiers: – Type: issn-print Value: 08821666 Numbering: – Type: volume Value: 36 – Type: issue Value: 9 Titles: – TitleFull: Systems & Computers in Japan Type: main |
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