RMSRM: real-time monitoring-based self-reconfiguration mechanism in reconfigurable PE array.
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| Title: | RMSRM: real-time monitoring-based self-reconfiguration mechanism in reconfigurable PE array. |
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| Authors: | Yang, Kun1,2 (AUTHOR), Jiang, Lin2 (AUTHOR) jianglin@xust.edu.cn, Shan, Rui3 (AUTHOR), Li, Kangle1,2 (AUTHOR), Cui, Xinyue3 (AUTHOR) |
| Source: | Journal of Supercomputing. Mar2024, Vol. 80 Issue 5, p7071-7101. 31p. |
| Subjects: | Programmable controllers, Client/server computing equipment, Array processing, Energy consumption, Logic circuits |
| Abstract: | Modern applications need to flexibly adjust the processing process according to the different environments and real-time processing, thus putting forward higher requirements for the reconfiguration performance of coarse-grained reconfigurable architecture (CGRA). Traditional dynamic reconfiguration requires constant configuration of the processor by the host computer. Still, this reconfiguration method severely restricts switching different tasks, making it difficult to achieve dynamic real-time reconfiguration and limiting performance improvement. This paper presents a real-time monitoring-based self-reconfiguration mechanism (RMSRM) based on the implementation of CGRA. This mechanism improves the reconfiguration performance by monitoring the execution process of the array in real-time through a programmable controller on the basis of the homogeneous processing element (PE) array and dynamic scheduling of PE array resources according to different application requirements. The proposed RMSRM is capable of feeding array execution state information to the programmable controller within 1 clock cycle, switching configurations between different tasks within 10 clock cycles, and shutting down the unnecessary PE/PEs according to the current configuration. To verify the correctness and efficiency, we model hardware with synthesizable RTL coding and implement it on FPGA and a chip. The experimental results show that RMSRM can effectively reduce the reconfiguration overhead compared with traditional reconfiguration methods. The volume of bits in the configuration file has decreased by an average of 39.37%, and the reconfiguration time has decreased by an average of 43.57%. Based on the SMIC 55nm process, the operating frequency can reach 320 MHz. Meanwhile, the resource consumption is 80506 logic gates, the chip area is 12 mm 2 , and the energy efficiency is 312 GOPS/W. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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| Abstract: | Modern applications need to flexibly adjust the processing process according to the different environments and real-time processing, thus putting forward higher requirements for the reconfiguration performance of coarse-grained reconfigurable architecture (CGRA). Traditional dynamic reconfiguration requires constant configuration of the processor by the host computer. Still, this reconfiguration method severely restricts switching different tasks, making it difficult to achieve dynamic real-time reconfiguration and limiting performance improvement. This paper presents a real-time monitoring-based self-reconfiguration mechanism (RMSRM) based on the implementation of CGRA. This mechanism improves the reconfiguration performance by monitoring the execution process of the array in real-time through a programmable controller on the basis of the homogeneous processing element (PE) array and dynamic scheduling of PE array resources according to different application requirements. The proposed RMSRM is capable of feeding array execution state information to the programmable controller within 1 clock cycle, switching configurations between different tasks within 10 clock cycles, and shutting down the unnecessary PE/PEs according to the current configuration. To verify the correctness and efficiency, we model hardware with synthesizable RTL coding and implement it on FPGA and a chip. The experimental results show that RMSRM can effectively reduce the reconfiguration overhead compared with traditional reconfiguration methods. The volume of bits in the configuration file has decreased by an average of 39.37%, and the reconfiguration time has decreased by an average of 43.57%. Based on the SMIC 55nm process, the operating frequency can reach 320 MHz. Meanwhile, the resource consumption is 80506 logic gates, the chip area is 12 mm 2 , and the energy efficiency is 312 GOPS/W. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 09208542 |
| DOI: | 10.1007/s11227-023-05707-0 |
