MOSAIC: Maximizing ResOurce Sharing in Behavioral Application SpecIfic ProCessors.
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| Title: | MOSAIC: Maximizing ResOurce Sharing in Behavioral Application SpecIfic ProCessors. |
|---|---|
| Authors: | Si, Qilin1 (AUTHOR) siyuan.xu@utdallas.edu, Carrion Schafer, Benjamin1 (AUTHOR) schaferb@utdallas.edu |
| Source: | Microprocessors & Microsystems. Apr2024, Vol. 106, pN.PAG-N.PAG. 1p. |
| Subjects: | Application-specific instruction-set processors |
| Abstract: | This work presents a method that can quickly determine which hardware accelerators (HWaccs) should be mapped together onto an Application-Specific Instruction Set Processor (ASIP), such that the resources shared among them are maximized. This work in particular targets HWaccs generated from untimed behavioral descriptions for High-Level Synthesis (HLS). Although HLS is a single process synthesis method, our approach is able to force resource sharing among the HWaccs by combining their behavioral descriptions together into a single description based on their potential to share resources. These shared resources include functional units (FUs) like multipliers, adders, and dividers, and also registers. In particular, our proposed flow leads up to 48% in area savings and on average 30%. Because an exhaustive enumeration of all possible combinations can lead to long runtimes, we propose a fast heuristic that leads to comparable results (only 6% worse on average), while being much faster (on average 500 ×). [ABSTRACT FROM AUTHOR] |
| Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 176612469 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: MOSAIC: Maximizing ResOurce Sharing in Behavioral Application SpecIfic ProCessors. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Si%2C+Qilin%22">Si, Qilin</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> siyuan.xu@utdallas.edu</i><br /><searchLink fieldCode="AR" term="%22Carrion+Schafer%2C+Benjamin%22">Carrion Schafer, Benjamin</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> schaferb@utdallas.edu</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Microprocessors+%26+Microsystems%22">Microprocessors & Microsystems</searchLink>. Apr2024, Vol. 106, pN.PAG-N.PAG. 1p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Application-specific+instruction-set+processors%22">Application-specific instruction-set processors</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: This work presents a method that can quickly determine which hardware accelerators (HWaccs) should be mapped together onto an Application-Specific Instruction Set Processor (ASIP), such that the resources shared among them are maximized. This work in particular targets HWaccs generated from untimed behavioral descriptions for High-Level Synthesis (HLS). Although HLS is a single process synthesis method, our approach is able to force resource sharing among the HWaccs by combining their behavioral descriptions together into a single description based on their potential to share resources. These shared resources include functional units (FUs) like multipliers, adders, and dividers, and also registers. In particular, our proposed flow leads up to 48% in area savings and on average 30%. Because an exhaustive enumeration of all possible combinations can lead to long runtimes, we propose a fast heuristic that leads to comparable results (only 6% worse on average), while being much faster (on average 500 ×). [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=176612469 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1016/j.micpro.2024.105039 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 1 StartPage: N.PAG Subjects: – SubjectFull: Application-specific instruction-set processors Type: general Titles: – TitleFull: MOSAIC: Maximizing ResOurce Sharing in Behavioral Application SpecIfic ProCessors. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Si, Qilin – PersonEntity: Name: NameFull: Carrion Schafer, Benjamin IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 04 Text: Apr2024 Type: published Y: 2024 Identifiers: – Type: issn-print Value: 01419331 Numbering: – Type: volume Value: 106 Titles: – TitleFull: Microprocessors & Microsystems Type: main |
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