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A 3-D Bank Memory System for Low-Power Neural Network Processing Achieved by Instant Context Switching and Extended Power Gating Time.

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Title: A 3-D Bank Memory System for Low-Power Neural Network Processing Achieved by Instant Context Switching and Extended Power Gating Time.
Authors: Toyotaka, Kouhei1 (AUTHOR) kt1024@sel.co.jp, Yakubo, Yuto1 (AUTHOR), Furutani, Kazuma1 (AUTHOR), Katagiri, Haruki2 (AUTHOR), Fujita, Masashi1 (AUTHOR), Ando, Yoshinori3 (AUTHOR), Nakura, Toru4 (AUTHOR), Yamazaki, Shunpei5 (AUTHOR)
Source: Computing in Science & Engineering. Jan-Mar2024, Vol. 26 Issue 1, p486-494. 9p.
Subjects: Static random access memory chips, Semiconductors
Abstract: Using a 3-D monolithic stacking memory technology of crystalline oxide semiconductor (OS) transistors, we fabricated a test chip having AI accelerator (ACC) memory for weight data of a neural network (NN), backup memory of flip-flops (FF), and CPU memory storing instructions and data. These memories are composed of two-layer OS transistors on Si CMOS, where memories in each layer correspond to a bank. In this structure, bank switching of the ACC memory and the FF backup memory work together, and thus inference of different NNs is switched with low latency and low power so that the power gating standby time can be extended. Consequently, a 92% reduction in power consumption is achieved in inference at a frame rate of 60 fps as compared with a chip using static random access memory (SRAM) as the ACC memory. [ABSTRACT FROM AUTHOR]
Copyright of Computing in Science & Engineering is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: A 3-D Bank Memory System for Low-Power Neural Network Processing Achieved by Instant Context Switching and Extended Power Gating Time.
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  Data: <searchLink fieldCode="AR" term="%22Toyotaka%2C+Kouhei%22">Toyotaka, Kouhei</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> kt1024@sel.co.jp</i><br /><searchLink fieldCode="AR" term="%22Yakubo%2C+Yuto%22">Yakubo, Yuto</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Furutani%2C+Kazuma%22">Furutani, Kazuma</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Katagiri%2C+Haruki%22">Katagiri, Haruki</searchLink><relatesTo>2</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Fujita%2C+Masashi%22">Fujita, Masashi</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Ando%2C+Yoshinori%22">Ando, Yoshinori</searchLink><relatesTo>3</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Nakura%2C+Toru%22">Nakura, Toru</searchLink><relatesTo>4</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Yamazaki%2C+Shunpei%22">Yamazaki, Shunpei</searchLink><relatesTo>5</relatesTo> (AUTHOR)
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  Data: <searchLink fieldCode="JN" term="%22Computing+in+Science+%26+Engineering%22">Computing in Science & Engineering</searchLink>. Jan-Mar2024, Vol. 26 Issue 1, p486-494. 9p.
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  Data: Using a 3-D monolithic stacking memory technology of crystalline oxide semiconductor (OS) transistors, we fabricated a test chip having AI accelerator (ACC) memory for weight data of a neural network (NN), backup memory of flip-flops (FF), and CPU memory storing instructions and data. These memories are composed of two-layer OS transistors on Si CMOS, where memories in each layer correspond to a bank. In this structure, bank switching of the ACC memory and the FF backup memory work together, and thus inference of different NNs is switched with low latency and low power so that the power gating standby time can be extended. Consequently, a 92% reduction in power consumption is achieved in inference at a frame rate of 60 fps as compared with a chip using static random access memory (SRAM) as the ACC memory. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of Computing in Science & Engineering is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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              Text: Jan-Mar2024
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