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Expanding the time-interleaving design capabilities: A 28 GS/s 4-bit time-interleaved current-steering DAC case study.

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Title: Expanding the time-interleaving design capabilities: A 28 GS/s 4-bit time-interleaved current-steering DAC case study.
Authors: Michailidis, Anastasios1 (AUTHOR) anamicha@physics.auth.gr, Noulis, Thomas1 (AUTHOR), Pavlidis, Vasileios2 (AUTHOR)
Source: AEU: International Journal of Electronics & Communications. Aug2024, Vol. 183, pN.PAG-N.PAG. 1p.
Subjects: Digital-to-analog converters, Complementary metal oxide semiconductors, Superposition principle (Physics)
Abstract: In this work, a novel approach of designing high-speed time-interleaved Digital-to-Analog Converters (DACs), that exploits high-order time-interleaved factors, was proposed. The presented time-interleaving design approach is based on the current superposition principle, capable of expanding the time-interleaved factor of DACs without compromising the conversion linearity and accuracy. For the validation of the proposed design approach, a 28 GS/s 4-bit 4 × Time-Interleaved current-steering DAC was designed using a 22 nm Fully-Depleted Silicon-On-Insulator (FDSOI) CMOS process node. Post-layout simulations were carried out by developing a custom, hybrid RC/RLCk parasitic extraction methodology, capable of capturing all possible layout parasitic effects due to the high conversion speed of the designed DAC. Using the proposed approach, the designed time-interleaved DAC was capable of achieving E N O B > 3. 83 bits, S F D R > 28. 7 dBc for f i n ≤ 1. 75 GHz, with no missing codes and a low power consumption of P d i s s = 3. 1 mW/core. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:In this work, a novel approach of designing high-speed time-interleaved Digital-to-Analog Converters (DACs), that exploits high-order time-interleaved factors, was proposed. The presented time-interleaving design approach is based on the current superposition principle, capable of expanding the time-interleaved factor of DACs without compromising the conversion linearity and accuracy. For the validation of the proposed design approach, a 28 GS/s 4-bit 4 × Time-Interleaved current-steering DAC was designed using a 22 nm Fully-Depleted Silicon-On-Insulator (FDSOI) CMOS process node. Post-layout simulations were carried out by developing a custom, hybrid RC/RLCk parasitic extraction methodology, capable of capturing all possible layout parasitic effects due to the high conversion speed of the designed DAC. Using the proposed approach, the designed time-interleaved DAC was capable of achieving E N O B > 3. 83 bits, S F D R > 28. 7 dBc for f i n ≤ 1. 75 GHz, with no missing codes and a low power consumption of P d i s s = 3. 1 mW/core. [ABSTRACT FROM AUTHOR]
ISSN:14348411
DOI:10.1016/j.aeue.2024.155399