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Expanding the time-interleaving design capabilities: A 28 GS/s 4-bit time-interleaved current-steering DAC case study.

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Title: Expanding the time-interleaving design capabilities: A 28 GS/s 4-bit time-interleaved current-steering DAC case study.
Authors: Michailidis, Anastasios1 (AUTHOR) anamicha@physics.auth.gr, Noulis, Thomas1 (AUTHOR), Pavlidis, Vasileios2 (AUTHOR)
Source: AEU: International Journal of Electronics & Communications. Aug2024, Vol. 183, pN.PAG-N.PAG. 1p.
Subjects: Digital-to-analog converters, Complementary metal oxide semiconductors, Superposition principle (Physics)
Abstract: In this work, a novel approach of designing high-speed time-interleaved Digital-to-Analog Converters (DACs), that exploits high-order time-interleaved factors, was proposed. The presented time-interleaving design approach is based on the current superposition principle, capable of expanding the time-interleaved factor of DACs without compromising the conversion linearity and accuracy. For the validation of the proposed design approach, a 28 GS/s 4-bit 4 × Time-Interleaved current-steering DAC was designed using a 22 nm Fully-Depleted Silicon-On-Insulator (FDSOI) CMOS process node. Post-layout simulations were carried out by developing a custom, hybrid RC/RLCk parasitic extraction methodology, capable of capturing all possible layout parasitic effects due to the high conversion speed of the designed DAC. Using the proposed approach, the designed time-interleaved DAC was capable of achieving E N O B > 3. 83 bits, S F D R > 28. 7 dBc for f i n ≤ 1. 75 GHz, with no missing codes and a low power consumption of P d i s s = 3. 1 mW/core. [ABSTRACT FROM AUTHOR]
Copyright of AEU: International Journal of Electronics & Communications is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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DbLabel: Engineering Source
An: 178537813
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  Data: Expanding the time-interleaving design capabilities: A 28 GS/s 4-bit time-interleaved current-steering DAC case study.
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  Data: <searchLink fieldCode="AR" term="%22Michailidis%2C+Anastasios%22">Michailidis, Anastasios</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> anamicha@physics.auth.gr</i><br /><searchLink fieldCode="AR" term="%22Noulis%2C+Thomas%22">Noulis, Thomas</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Pavlidis%2C+Vasileios%22">Pavlidis, Vasileios</searchLink><relatesTo>2</relatesTo> (AUTHOR)
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  Data: <searchLink fieldCode="JN" term="%22AEU%3A+International+Journal+of+Electronics+%26+Communications%22">AEU: International Journal of Electronics & Communications</searchLink>. Aug2024, Vol. 183, pN.PAG-N.PAG. 1p.
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  Data: <searchLink fieldCode="DE" term="%22Digital-to-analog+converters%22">Digital-to-analog converters</searchLink><br /><searchLink fieldCode="DE" term="%22Complementary+metal+oxide+semiconductors%22">Complementary metal oxide semiconductors</searchLink><br /><searchLink fieldCode="DE" term="%22Superposition+principle+%28Physics%29%22">Superposition principle (Physics)</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: In this work, a novel approach of designing high-speed time-interleaved Digital-to-Analog Converters (DACs), that exploits high-order time-interleaved factors, was proposed. The presented time-interleaving design approach is based on the current superposition principle, capable of expanding the time-interleaved factor of DACs without compromising the conversion linearity and accuracy. For the validation of the proposed design approach, a 28 GS/s 4-bit 4 × Time-Interleaved current-steering DAC was designed using a 22 nm Fully-Depleted Silicon-On-Insulator (FDSOI) CMOS process node. Post-layout simulations were carried out by developing a custom, hybrid RC/RLCk parasitic extraction methodology, capable of capturing all possible layout parasitic effects due to the high conversion speed of the designed DAC. Using the proposed approach, the designed time-interleaved DAC was capable of achieving E N O B > 3. 83 bits, S F D R > 28. 7 dBc for f i n ≤ 1. 75 GHz, with no missing codes and a low power consumption of P d i s s = 3. 1 mW/core. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of AEU: International Journal of Electronics & Communications is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1016/j.aeue.2024.155399
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        Text: English
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        Type: general
      – SubjectFull: Complementary metal oxide semiconductors
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      – SubjectFull: Superposition principle (Physics)
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      – TitleFull: Expanding the time-interleaving design capabilities: A 28 GS/s 4-bit time-interleaved current-steering DAC case study.
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              M: 08
              Text: Aug2024
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