Design and analysis of carrier reservoir SOA based 2 × 1 MUX with enable input and implementing basic logic gates using MUX at 120 Gb/s.

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Title: Design and analysis of carrier reservoir SOA based 2 × 1 MUX with enable input and implementing basic logic gates using MUX at 120 Gb/s.
Authors: Agarwal, Vipul1 (AUTHOR) agarvipul@gmail.com, Pareek, Prakash2 (AUTHOR) ppareek1@gmail.com, Gupta, Sumit3 (AUTHOR), Singh, Lokendra4 (AUTHOR), Balaji, Bukya1 (AUTHOR), Dakua, Pratap Kumar5 (AUTHOR)
Source: Optical & Quantum Electronics. Sep2024, Vol. 56 Issue 9, p1-29. 29p.
Subjects: Semiconductor optical amplifiers, Quality factor, Logic circuits, Routing systems
Abstract: In this paper, carrier reservoir semiconductor optical amplifiers (CR-SOAs) are utilized for the first time in designing an all-optical 2 × 1 multiplexer with enable function, operating at 120 Gb/s. Traditional SOAs face challenges with slow carrier recovery, restricting their application in high-speed scenarios. CR-SOA, with a carrier reservoir near the active region, replenishes carriers quickly, enabling faster gain and phase recovery. For the first time, a 2 × 1 multiplexer with an enable input is proposed, adding flexibility and control for dynamic data routing in optical systems. Basic gates such as AND, OR, and NOT gates have been designed using this multiplexer, with the enable input enhancing their versatility. The performance of the multiplexer and gates is evaluated using metrics like quality factor, extinction ratio, contrast ratio, and eye opening factor. The quality factor is analyzed concerning parameters such as amplified spontaneous emission, data rate, carrier transition time, and injection current. Simulation results confirm the functionality of the 2 × 1 multiplexer and logic gates, demonstrating satisfactory performance at high data rates. [ABSTRACT FROM AUTHOR]
Copyright of Optical & Quantum Electronics is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: Design and analysis of carrier reservoir SOA based 2 × 1 MUX with enable input and implementing basic logic gates using MUX at 120 Gb/s.
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  Data: <searchLink fieldCode="JN" term="%22Optical+%26+Quantum+Electronics%22">Optical & Quantum Electronics</searchLink>. Sep2024, Vol. 56 Issue 9, p1-29. 29p.
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  Data: <searchLink fieldCode="DE" term="%22Semiconductor+optical+amplifiers%22">Semiconductor optical amplifiers</searchLink><br /><searchLink fieldCode="DE" term="%22Quality+factor%22">Quality factor</searchLink><br /><searchLink fieldCode="DE" term="%22Logic+circuits%22">Logic circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Routing+systems%22">Routing systems</searchLink>
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  Data: In this paper, carrier reservoir semiconductor optical amplifiers (CR-SOAs) are utilized for the first time in designing an all-optical 2 × 1 multiplexer with enable function, operating at 120 Gb/s. Traditional SOAs face challenges with slow carrier recovery, restricting their application in high-speed scenarios. CR-SOA, with a carrier reservoir near the active region, replenishes carriers quickly, enabling faster gain and phase recovery. For the first time, a 2 × 1 multiplexer with an enable input is proposed, adding flexibility and control for dynamic data routing in optical systems. Basic gates such as AND, OR, and NOT gates have been designed using this multiplexer, with the enable input enhancing their versatility. The performance of the multiplexer and gates is evaluated using metrics like quality factor, extinction ratio, contrast ratio, and eye opening factor. The quality factor is analyzed concerning parameters such as amplified spontaneous emission, data rate, carrier transition time, and injection current. Simulation results confirm the functionality of the 2 × 1 multiplexer and logic gates, demonstrating satisfactory performance at high data rates. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Optical & Quantum Electronics is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1007/s11082-024-07351-1
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        Text: English
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      – SubjectFull: Quality factor
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      – SubjectFull: Logic circuits
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            – D: 01
              M: 09
              Text: Sep2024
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              Y: 2024
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