A New Highly Linear Current-to-Time Converter for Direct Sensing Applications.
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| Title: | A New Highly Linear Current-to-Time Converter for Direct Sensing Applications. |
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| Authors: | Al-Absi, Munir1,2 (AUTHOR) mkulaib@kfupm.edu.sa, Al-Khulaifi, Abdulaziz1 (AUTHOR), Mahnashi, Yaqub1,2,3 (AUTHOR) |
| Source: | Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ). Dec2024, Vol. 49 Issue 12, p17023-17029. 7p. |
| Subjects: | Data conversion, Analog-to-digital converters, Inverse functions, Block designs, Consumption (Economics) |
| Abstract: | The growing interest in time-based analog-to-digital converters is primarily driven by their ability to achieve high speed and low power consumption. The signal-to-time converter is one of the main components of these converters. However, designing this block is challenging due to the strict requirement for good linearity. This paper introduces a new design concept to devise a highly linear signal-to-time converter that utilizes the inverse function of the signal, which is current in this study. Using the concept of inverse function, the delay becomes directly proportional to the input signal, resulting in a significant improvement in the linearity of the circuit. The proposed design is implemented using 0.18 μ m TSMC CMOS technology and is validated through post-layout simulations conducted in Cadence Virtuoso environment. The circuit is powered by 1.8 V and tested with an input current that ranges from 1–30 nA. The power consumption is measured for the full range of the input current, 1–30 nA, and it shows a peak of 19.6 μ W power consumption when processing a 30 nA input current. The simulation results confirm the functionality of the proposed design, with a conversion gain of 1.8 ns/nA and a maximum error of 3.5 % observed between the pre-layout and post-layout simulations. [ABSTRACT FROM AUTHOR] |
| Copyright of Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ) is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Abstract: | The growing interest in time-based analog-to-digital converters is primarily driven by their ability to achieve high speed and low power consumption. The signal-to-time converter is one of the main components of these converters. However, designing this block is challenging due to the strict requirement for good linearity. This paper introduces a new design concept to devise a highly linear signal-to-time converter that utilizes the inverse function of the signal, which is current in this study. Using the concept of inverse function, the delay becomes directly proportional to the input signal, resulting in a significant improvement in the linearity of the circuit. The proposed design is implemented using 0.18 μ m TSMC CMOS technology and is validated through post-layout simulations conducted in Cadence Virtuoso environment. The circuit is powered by 1.8 V and tested with an input current that ranges from 1–30 nA. The power consumption is measured for the full range of the input current, 1–30 nA, and it shows a peak of 19.6 μ W power consumption when processing a 30 nA input current. The simulation results confirm the functionality of the proposed design, with a conversion gain of 1.8 ns/nA and a maximum error of 3.5 % observed between the pre-layout and post-layout simulations. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 2193567X |
| DOI: | 10.1007/s13369-024-09458-9 |
