Design of decryption process for advanced encryption standard algorithm in system-on-chip.

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Bibliographic Details
Title:	Design of decryption process for advanced encryption standard algorithm in system-on-chip.
Authors:	Prathap, Joseph Anthony¹ japtuhi1116@gmail.com, Raj, Mrinal² mrinalraj12@gmail.com, Patnaik, Ritu¹ ritu.pnaik@gmail.com
Source:	International Journal of Electrical & Computer Engineering (2088-8708). Dec2024, Vol. 14 Issue 6, p6838-6845. 8p.
Subjects:	Advanced Encryption Standard, Computer hardware description languages, Integrated circuit layout, Electronic design automation, Gate array circuits
Abstract:	This paper concentrates on the development of system-on-chip for the decryption algorithm in the advanced encryption standard (AES). This method includes the transformation of cipher text into plain text and consists of 4 sub-tasks based on the resolution. In this work, the 128-bit resolution is utilized to perform 10 rounds of transformation with the round key added at every round generated by the key expansion algorithm. Though there are many cryptography algorithms, the AES is simple, secure, faster in operation, and easy to develop compared to the others. The system-on-chip (SOC) design for the decryption of the AES depends on the synthesizable hardware description language (HDL) code development for all 10 rounds of processes with the key expansion algorithm. The lookup tables (LUTs) are used for the inverse S-box in the HDL code. The proposed SOC is designed using the Cadence electronic design automation (EDA) tools by making use of the synthesized HDL code for the proposed methods and analyzed for the very large-scale integration (VLSI) parameters. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	This paper concentrates on the development of system-on-chip for the decryption algorithm in the advanced encryption standard (AES). This method includes the transformation of cipher text into plain text and consists of 4 sub-tasks based on the resolution. In this work, the 128-bit resolution is utilized to perform 10 rounds of transformation with the round key added at every round generated by the key expansion algorithm. Though there are many cryptography algorithms, the AES is simple, secure, faster in operation, and easy to develop compared to the others. The system-on-chip (SOC) design for the decryption of the AES depends on the synthesizable hardware description language (HDL) code development for all 10 rounds of processes with the key expansion algorithm. The lookup tables (LUTs) are used for the inverse S-box in the HDL code. The proposed SOC is designed using the Cadence electronic design automation (EDA) tools by making use of the synthesized HDL code for the proposed methods and analyzed for the very large-scale integration (VLSI) parameters. [ABSTRACT FROM AUTHOR]
ISSN:	20888708
DOI:	10.11591/ijece.v14i6.pp6838-6845