Design of decryption process for advanced encryption standard algorithm in system-on-chip.
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| Title: | Design of decryption process for advanced encryption standard algorithm in system-on-chip. |
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| Authors: | Prathap, Joseph Anthony1 japtuhi1116@gmail.com, Raj, Mrinal2 mrinalraj12@gmail.com, Patnaik, Ritu1 ritu.pnaik@gmail.com |
| Source: | International Journal of Electrical & Computer Engineering (2088-8708). Dec2024, Vol. 14 Issue 6, p6838-6845. 8p. |
| Subjects: | Advanced Encryption Standard, Computer hardware description languages, Integrated circuit layout, Electronic design automation, Gate array circuits |
| Abstract: | This paper concentrates on the development of system-on-chip for the decryption algorithm in the advanced encryption standard (AES). This method includes the transformation of cipher text into plain text and consists of 4 sub-tasks based on the resolution. In this work, the 128-bit resolution is utilized to perform 10 rounds of transformation with the round key added at every round generated by the key expansion algorithm. Though there are many cryptography algorithms, the AES is simple, secure, faster in operation, and easy to develop compared to the others. The system-on-chip (SOC) design for the decryption of the AES depends on the synthesizable hardware description language (HDL) code development for all 10 rounds of processes with the key expansion algorithm. The lookup tables (LUTs) are used for the inverse S-box in the HDL code. The proposed SOC is designed using the Cadence electronic design automation (EDA) tools by making use of the synthesized HDL code for the proposed methods and analyzed for the very large-scale integration (VLSI) parameters. [ABSTRACT FROM AUTHOR] |
| Copyright of International Journal of Electrical & Computer Engineering (2088-8708) is the property of Institute of Advanced Engineering & Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 180164553 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Design of decryption process for advanced encryption standard algorithm in system-on-chip. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Prathap%2C+Joseph+Anthony%22">Prathap, Joseph Anthony</searchLink><relatesTo>1</relatesTo><i> japtuhi1116@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Raj%2C+Mrinal%22">Raj, Mrinal</searchLink><relatesTo>2</relatesTo><i> mrinalraj12@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Patnaik%2C+Ritu%22">Patnaik, Ritu</searchLink><relatesTo>1</relatesTo><i> ritu.pnaik@gmail.com</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22International+Journal+of+Electrical+%26+Computer+Engineering+%282088-8708%29%22">International Journal of Electrical & Computer Engineering (2088-8708)</searchLink>. Dec2024, Vol. 14 Issue 6, p6838-6845. 8p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Advanced+Encryption+Standard%22">Advanced Encryption Standard</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+hardware+description+languages%22">Computer hardware description languages</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuit+layout%22">Integrated circuit layout</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+design+automation%22">Electronic design automation</searchLink><br /><searchLink fieldCode="DE" term="%22Gate+array+circuits%22">Gate array circuits</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: This paper concentrates on the development of system-on-chip for the decryption algorithm in the advanced encryption standard (AES). This method includes the transformation of cipher text into plain text and consists of 4 sub-tasks based on the resolution. In this work, the 128-bit resolution is utilized to perform 10 rounds of transformation with the round key added at every round generated by the key expansion algorithm. Though there are many cryptography algorithms, the AES is simple, secure, faster in operation, and easy to develop compared to the others. The system-on-chip (SOC) design for the decryption of the AES depends on the synthesizable hardware description language (HDL) code development for all 10 rounds of processes with the key expansion algorithm. The lookup tables (LUTs) are used for the inverse S-box in the HDL code. The proposed SOC is designed using the Cadence electronic design automation (EDA) tools by making use of the synthesized HDL code for the proposed methods and analyzed for the very large-scale integration (VLSI) parameters. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of International Journal of Electrical & Computer Engineering (2088-8708) is the property of Institute of Advanced Engineering & Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.11591/ijece.v14i6.pp6838-6845 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 8 StartPage: 6838 Subjects: – SubjectFull: Advanced Encryption Standard Type: general – SubjectFull: Computer hardware description languages Type: general – SubjectFull: Integrated circuit layout Type: general – SubjectFull: Electronic design automation Type: general – SubjectFull: Gate array circuits Type: general Titles: – TitleFull: Design of decryption process for advanced encryption standard algorithm in system-on-chip. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Prathap, Joseph Anthony – PersonEntity: Name: NameFull: Raj, Mrinal – PersonEntity: Name: NameFull: Patnaik, Ritu IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 12 Text: Dec2024 Type: published Y: 2024 Identifiers: – Type: issn-print Value: 20888708 Numbering: – Type: volume Value: 14 – Type: issue Value: 6 Titles: – TitleFull: International Journal of Electrical & Computer Engineering (2088-8708) Type: main |
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