APA (7th ed.) Citation

Basiri, M. M. A. (2025). High Throughput Instruction-Data Level Parallelism Based Arithmetic Hardware Accelerator. International Journal of Parallel Programming, 53(2), 1. https://doi.org/10.1007/s10766-025-00782-7

Chicago Style (17th ed.) Citation

Basiri, M. Mohamed Asan. "High Throughput Instruction-Data Level Parallelism Based Arithmetic Hardware Accelerator." International Journal of Parallel Programming 53, no. 2 (2025): 1. https://doi.org/10.1007/s10766-025-00782-7.

MLA (9th ed.) Citation

Basiri, M. Mohamed Asan. "High Throughput Instruction-Data Level Parallelism Based Arithmetic Hardware Accelerator." International Journal of Parallel Programming, vol. 53, no. 2, 2025, p. 1, https://doi.org/10.1007/s10766-025-00782-7.