High Throughput Instruction-Data Level Parallelism Based Arithmetic Hardware Accelerator.
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| Title: | High Throughput Instruction-Data Level Parallelism Based Arithmetic Hardware Accelerator. |
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| Authors: | Basiri, M. Mohamed Asan1 (AUTHOR) asan@iiitk.ac.in |
| Source: | International Journal of Parallel Programming. Apr2025, Vol. 53 Issue 2, p1-30. 30p. |
| Subjects: | Parallel processing, Floating-point arithmetic, Video processing, Image processing, Multiplication |
| Abstract: | The hardware accelerators play a major role in engineering applications such as image processing, video processing, cryptography, neural networks, and so on. This article proposes a high throughput instruction-data level parallelism based 32-bit hardware accelerator, where we can perform fixed/floating point addition, subtraction, multiplication, multiply-accumulation, division, logical operation, right/left shift, and the special operations (such as sin(x), cos(x), sinh(x), cosh(x), atanh(x), e x , and ln(x)) using CORDIC. In the proposed hardware accelerator, at most four non-similar operations, for example 32-bit fixed point addition, single precision floating point multiplication, single precision floating point e x , and 32-bit right shift can be performed in parallel. It is known as the instruction level parallelism. Also, multiple less precision similar operations, for example four 8-bit fixed point additions, two 16-bit left shifts, two 16-bit subtractions, and two 32 × 16 -bit fixed point multiply-accumulations can be done in parallel, where the non-similar functional units such as fixed point adder, left shifter, fixed point subtractor, and fixed point multiply-accumulator perform these operations respectively. It is known as data level parallelism. The novelty of our proposed 32-bit implementation is that both the instruction and data level parallelisms can be done in parallel. Hence, the throughput can be improved significantly. To achieve the data level parallelism, we propose variable precision 32-bit fixed point subtractor, 32-bit right shifter, and 32-bit left shifter, where one, two, and four numbers of 32-bit, 16-bit, and 8-bit operations can be done in parallel respectively. All the existing and proposed hardware accelerators are implemented in 45 nm CMOS technology. The synthesis results show that the proposed 32-bit hardware accelerator achieves at least 30 % of improvement in throughput compared with various existing designs. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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| Abstract: | The hardware accelerators play a major role in engineering applications such as image processing, video processing, cryptography, neural networks, and so on. This article proposes a high throughput instruction-data level parallelism based 32-bit hardware accelerator, where we can perform fixed/floating point addition, subtraction, multiplication, multiply-accumulation, division, logical operation, right/left shift, and the special operations (such as sin(x), cos(x), sinh(x), cosh(x), atanh(x), e x , and ln(x)) using CORDIC. In the proposed hardware accelerator, at most four non-similar operations, for example 32-bit fixed point addition, single precision floating point multiplication, single precision floating point e x , and 32-bit right shift can be performed in parallel. It is known as the instruction level parallelism. Also, multiple less precision similar operations, for example four 8-bit fixed point additions, two 16-bit left shifts, two 16-bit subtractions, and two 32 × 16 -bit fixed point multiply-accumulations can be done in parallel, where the non-similar functional units such as fixed point adder, left shifter, fixed point subtractor, and fixed point multiply-accumulator perform these operations respectively. It is known as data level parallelism. The novelty of our proposed 32-bit implementation is that both the instruction and data level parallelisms can be done in parallel. Hence, the throughput can be improved significantly. To achieve the data level parallelism, we propose variable precision 32-bit fixed point subtractor, 32-bit right shifter, and 32-bit left shifter, where one, two, and four numbers of 32-bit, 16-bit, and 8-bit operations can be done in parallel respectively. All the existing and proposed hardware accelerators are implemented in 45 nm CMOS technology. The synthesis results show that the proposed 32-bit hardware accelerator achieves at least 30 % of improvement in throughput compared with various existing designs. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 08857458 |
| DOI: | 10.1007/s10766-025-00782-7 |
