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Time‐Domain ADPLL BPSK, QPSK, and 8PSK Demodulators.

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Title: Time‐Domain ADPLL BPSK, QPSK, and 8PSK Demodulators.
Authors: Khumsat, Phanumas1 (AUTHOR) phanumas.k@psu.ac.th, Koyphol, Thanabodee1 (AUTHOR), Thongruk, Tan1 (AUTHOR), Inyod, Tidarat1 (AUTHOR), Tripathi, Suman Lata1 (AUTHOR)
Source: Journal of Electrical & Computer Engineering. 5/23/2025, Vol. 2025, p1-15. 15p.
Subjects: Phase-locked loops, Signal sampling, Radio detectors, Demodulation, Multiplexing
Abstract: Time‐domain all‐digital‐phase‐locked‐loop phase‐shift‐keying (PSK) demodulators are proposed for BPSK, QPSK, and 8PSK signals. The demodulator architectures are highly suitable for low‐voltage nanoscale CMOS techology. Data‐bit extraction as well as phase control for loop locking can be effectively achieved in a time domain with simple logic operators such as positive‐edge‐trigger RESET/SET (pRSFF) and delay flip flops (DFF). Pulse width of the phase‐control signal is sampled and passed on to the digitally‐controlled oscillator (DCO) for frequency and phase adjustment. Two different phase control methods have been employed to appropriately alter a duty cycle of the phase‐control signal. The first option is performed by multiplexing a single‐phase DCO signal as selected by the extracted data bits. The second technique uses m DCO phases simultaneously for phase‐control detection with the incoming m‐PSK signal. This helps reduce the intertwined loop of the first method to a single‐loop structure. This modular BPSK, QPSK, and 8PSK demodulation concept has been successfully verified by measurement with discrete components at a carrier frequency of 100 kHz operating under a 5‐V supply. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Electrical & Computer Engineering is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Label: Title
  Group: Ti
  Data: Time‐Domain ADPLL BPSK, QPSK, and 8PSK Demodulators.
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  Data: <searchLink fieldCode="AR" term="%22Khumsat%2C+Phanumas%22">Khumsat, Phanumas</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> phanumas.k@psu.ac.th</i><br /><searchLink fieldCode="AR" term="%22Koyphol%2C+Thanabodee%22">Koyphol, Thanabodee</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Thongruk%2C+Tan%22">Thongruk, Tan</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Inyod%2C+Tidarat%22">Inyod, Tidarat</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Tripathi%2C+Suman+Lata%22">Tripathi, Suman Lata</searchLink><relatesTo>1</relatesTo> (AUTHOR)
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Electrical+%26+Computer+Engineering%22">Journal of Electrical & Computer Engineering</searchLink>. 5/23/2025, Vol. 2025, p1-15. 15p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Phase-locked+loops%22">Phase-locked loops</searchLink><br /><searchLink fieldCode="DE" term="%22Signal+sampling%22">Signal sampling</searchLink><br /><searchLink fieldCode="DE" term="%22Radio+detectors%22">Radio detectors</searchLink><br /><searchLink fieldCode="DE" term="%22Demodulation%22">Demodulation</searchLink><br /><searchLink fieldCode="DE" term="%22Multiplexing%22">Multiplexing</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: Time‐domain all‐digital‐phase‐locked‐loop phase‐shift‐keying (PSK) demodulators are proposed for BPSK, QPSK, and 8PSK signals. The demodulator architectures are highly suitable for low‐voltage nanoscale CMOS techology. Data‐bit extraction as well as phase control for loop locking can be effectively achieved in a time domain with simple logic operators such as positive‐edge‐trigger RESET/SET (pRSFF) and delay flip flops (DFF). Pulse width of the phase‐control signal is sampled and passed on to the digitally‐controlled oscillator (DCO) for frequency and phase adjustment. Two different phase control methods have been employed to appropriately alter a duty cycle of the phase‐control signal. The first option is performed by multiplexing a single‐phase DCO signal as selected by the extracted data bits. The second technique uses m DCO phases simultaneously for phase‐control detection with the incoming m‐PSK signal. This helps reduce the intertwined loop of the first method to a single‐loop structure. This modular BPSK, QPSK, and 8PSK demodulation concept has been successfully verified by measurement with discrete components at a carrier frequency of 100 kHz operating under a 5‐V supply. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Journal of Electrical & Computer Engineering is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1155/jece/5560884
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        Text: English
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        PageCount: 15
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        Type: general
      – SubjectFull: Signal sampling
        Type: general
      – SubjectFull: Radio detectors
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      – SubjectFull: Demodulation
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      – SubjectFull: Multiplexing
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      – TitleFull: Time‐Domain ADPLL BPSK, QPSK, and 8PSK Demodulators.
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            – D: 23
              M: 05
              Text: 5/23/2025
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              Y: 2025
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