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Tag Replication and Status Bits Encoding for Enhancing Cache Metadata Reliability.

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Title: Tag Replication and Status Bits Encoding for Enhancing Cache Metadata Reliability.
Authors: Tabbakh, Abdulaziz1 (AUTHOR) atabakh@kfupm.edu.sa, Tani, Andrea1 (AUTHOR)
Source: Journal of Electrical & Computer Engineering. 5/25/2025, Vol. 2025, p1-10. 10p.
Subjects: Data corruption, Appropriate technology, Encoding, Soft errors, Memory, Cache memory, Metadata, Tags (Metadata)
Abstract: On‐chip caches occupy a significant portion of modern processors, making them increasingly vulnerable to soft errors as technology scales. While data arrays often receive robust protection via error‐correcting codes (ECCs), metadata elements such as tag fields and status bits remain inadequately protected despite their critical role in ensuring memory integrity. This paper proposes two lightweight techniques to enhance cache metadata reliability: (1) a robust three‐bit encoding scheme for status bits that tolerates single‐bit flips without data corruption and (2) a selective tag replication scheme for dirty cache blocks, enabling reliable recovery from single‐bit errors in tag arrays. Simulation results on SPEC 2006 benchmarks show that our approach recovers 97.3% of injected soft errors in cache metadata, outperforming conventional SECDED protection (93.8%) with significantly lower overhead. The proposed design incurs only 0.50% area and 1.67% dynamic power overhead on a data L1 cache. Moreover, the proposed techniques can be extended to support common cache coherence protocols in multicore systems with minimal modification. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Electrical & Computer Engineering is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: Tag Replication and Status Bits Encoding for Enhancing Cache Metadata Reliability.
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Electrical+%26+Computer+Engineering%22">Journal of Electrical & Computer Engineering</searchLink>. 5/25/2025, Vol. 2025, p1-10. 10p.
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  Data: <searchLink fieldCode="DE" term="%22Data+corruption%22">Data corruption</searchLink><br /><searchLink fieldCode="DE" term="%22Appropriate+technology%22">Appropriate technology</searchLink><br /><searchLink fieldCode="DE" term="%22Encoding%22">Encoding</searchLink><br /><searchLink fieldCode="DE" term="%22Soft+errors%22">Soft errors</searchLink><br /><searchLink fieldCode="DE" term="%22Memory%22">Memory</searchLink><br /><searchLink fieldCode="DE" term="%22Cache+memory%22">Cache memory</searchLink><br /><searchLink fieldCode="DE" term="%22Metadata%22">Metadata</searchLink><br /><searchLink fieldCode="DE" term="%22Tags+%28Metadata%29%22">Tags (Metadata)</searchLink>
– Name: Abstract
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  Data: On‐chip caches occupy a significant portion of modern processors, making them increasingly vulnerable to soft errors as technology scales. While data arrays often receive robust protection via error‐correcting codes (ECCs), metadata elements such as tag fields and status bits remain inadequately protected despite their critical role in ensuring memory integrity. This paper proposes two lightweight techniques to enhance cache metadata reliability: (1) a robust three‐bit encoding scheme for status bits that tolerates single‐bit flips without data corruption and (2) a selective tag replication scheme for dirty cache blocks, enabling reliable recovery from single‐bit errors in tag arrays. Simulation results on SPEC 2006 benchmarks show that our approach recovers 97.3% of injected soft errors in cache metadata, outperforming conventional SECDED protection (93.8%) with significantly lower overhead. The proposed design incurs only 0.50% area and 1.67% dynamic power overhead on a data L1 cache. Moreover, the proposed techniques can be extended to support common cache coherence protocols in multicore systems with minimal modification. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
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  Data: <i>Copyright of Journal of Electrical & Computer Engineering is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1155/jece/5008986
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      – Code: eng
        Text: English
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      – SubjectFull: Data corruption
        Type: general
      – SubjectFull: Appropriate technology
        Type: general
      – SubjectFull: Encoding
        Type: general
      – SubjectFull: Soft errors
        Type: general
      – SubjectFull: Memory
        Type: general
      – SubjectFull: Cache memory
        Type: general
      – SubjectFull: Metadata
        Type: general
      – SubjectFull: Tags (Metadata)
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      – TitleFull: Tag Replication and Status Bits Encoding for Enhancing Cache Metadata Reliability.
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              M: 05
              Text: 5/25/2025
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