Experimental and numerical investigations on amalgamation of mixed frequency carrier based asymmetrical 15 level multilevel inverter.
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| Title: | Experimental and numerical investigations on amalgamation of mixed frequency carrier based asymmetrical 15 level multilevel inverter. |
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| Authors: | Paramasivan, Muthukumar1 (AUTHOR) muthukumarvlsi@gmail.com, Prasad, T. Narasimha2 (AUTHOR), Vanchinathan, K.3 (AUTHOR) |
| Source: | Electrical Engineering. May2025, Vol. 107 Issue 5, p5861-5875. 15p. |
| Subjects: | Metal oxide semiconductor field-effect transistors, Pulse width modulation inverters, Gate array circuits, Ideal sources (Electric circuits), Pulse width modulation |
| Abstract: | This research encompasses the investigations of a multicarrier based 15 level multilevel inverter in an asymmetrical mode. The series connection of three voltage sources (12 V, 24 V and 48 V) with three metal oxide semiconductor field effect transistor (MOSFET) switches and a parallel H-bridge are used to construct the multilevel inverter. The phase disposition configurations of triangle carrier and inverted sine carrier are selected for the investigations. The indigenous pulse-width modulation (PWM) has been generated for three series switches from the comparison of seven carriers with a reference. The two frequencies (1 kHz and 4 kHz) are chosen for carriers. The 4 kHz frequency carrier will be active only at the peak of the sine reference between 5π/12 ≥ θ ≤ 7π/12 in positive half cycle and between 17π/12 ≥ θ ≤ 19π/12 in negative half cycle, remaining period 1 kHz frequency carrier has been active. These schemes have been verified with single-phase MLI with RL load. The MATLAB-based simulation results of fours schemes are presented. A field-programmable gate array-based experimental result of best scheme among four is reported, and corresponding hardware results are evidenced. The Xilinx Vivado design suite has been used for design synthesis and bit file generation for the FPGA. [ABSTRACT FROM AUTHOR] |
| Copyright of Electrical Engineering is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
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| Header | DbId: egs DbLabel: Engineering Source An: 185942677 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Experimental and numerical investigations on amalgamation of mixed frequency carrier based asymmetrical 15 level multilevel inverter. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Paramasivan%2C+Muthukumar%22">Paramasivan, Muthukumar</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> muthukumarvlsi@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Prasad%2C+T%2E+Narasimha%22">Prasad, T. Narasimha</searchLink><relatesTo>2</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Vanchinathan%2C+K%2E%22">Vanchinathan, K.</searchLink><relatesTo>3</relatesTo> (AUTHOR) – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Electrical+Engineering%22">Electrical Engineering</searchLink>. May2025, Vol. 107 Issue 5, p5861-5875. 15p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Metal+oxide+semiconductor+field-effect+transistors%22">Metal oxide semiconductor field-effect transistors</searchLink><br /><searchLink fieldCode="DE" term="%22Pulse+width+modulation+inverters%22">Pulse width modulation inverters</searchLink><br /><searchLink fieldCode="DE" term="%22Gate+array+circuits%22">Gate array circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Ideal+sources+%28Electric+circuits%29%22">Ideal sources (Electric circuits)</searchLink><br /><searchLink fieldCode="DE" term="%22Pulse+width+modulation%22">Pulse width modulation</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: This research encompasses the investigations of a multicarrier based 15 level multilevel inverter in an asymmetrical mode. The series connection of three voltage sources (12 V, 24 V and 48 V) with three metal oxide semiconductor field effect transistor (MOSFET) switches and a parallel H-bridge are used to construct the multilevel inverter. The phase disposition configurations of triangle carrier and inverted sine carrier are selected for the investigations. The indigenous pulse-width modulation (PWM) has been generated for three series switches from the comparison of seven carriers with a reference. The two frequencies (1 kHz and 4 kHz) are chosen for carriers. The 4 kHz frequency carrier will be active only at the peak of the sine reference between 5π/12 ≥ θ ≤ 7π/12 in positive half cycle and between 17π/12 ≥ θ ≤ 19π/12 in negative half cycle, remaining period 1 kHz frequency carrier has been active. These schemes have been verified with single-phase MLI with RL load. The MATLAB-based simulation results of fours schemes are presented. A field-programmable gate array-based experimental result of best scheme among four is reported, and corresponding hardware results are evidenced. The Xilinx Vivado design suite has been used for design synthesis and bit file generation for the FPGA. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Electrical Engineering is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s00202-024-02854-2 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 15 StartPage: 5861 Subjects: – SubjectFull: Metal oxide semiconductor field-effect transistors Type: general – SubjectFull: Pulse width modulation inverters Type: general – SubjectFull: Gate array circuits Type: general – SubjectFull: Ideal sources (Electric circuits) Type: general – SubjectFull: Pulse width modulation Type: general Titles: – TitleFull: Experimental and numerical investigations on amalgamation of mixed frequency carrier based asymmetrical 15 level multilevel inverter. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Paramasivan, Muthukumar – PersonEntity: Name: NameFull: Prasad, T. Narasimha – PersonEntity: Name: NameFull: Vanchinathan, K. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 05 Text: May2025 Type: published Y: 2025 Identifiers: – Type: issn-print Value: 09487921 Numbering: – Type: volume Value: 107 – Type: issue Value: 5 Titles: – TitleFull: Electrical Engineering Type: main |
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