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Design, Verification and Hardware Implementation of 4kB Synchronous FIFO for Automatic Vehicle Communication Applications.

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Title: Design, Verification and Hardware Implementation of 4kB Synchronous FIFO for Automatic Vehicle Communication Applications.
Authors: Mathew, Ribu1 (AUTHOR) ribu.mathew@gmail.com, Maila, Madhushankara1 (AUTHOR) madhushankar.m@manipal.edu, Kulai, Trishal1 (AUTHOR) trishal.msismpl2023@learner.manipal.edu
Source: Journal of Circuits, Systems & Computers. 8/1/2025, Vol. 34 Issue 12, p1-13. 13p.
Subjects: Flow control (Data transmission systems), Integrated circuit verification, Data structures, First in, first out (Queuing theory), Statistical smoothing
Abstract: Sustainability in in-vehicle communication comprises the integration of wireless technology for faster and more reliable connectivity. Driverless vehicles need to schedule various tasks on a priority basis. The first-in-first-out (FIFO) data structure is critical for handling sensor data and communication information, and a memory queue is important for controlling data flow through organized read and write processes. This study focuses on the design, verification and synthesis of a FIFO with a size of 4k bytes. By operating on a single clock signal, synchronous FIFO enables smooth data transmission between a source and destination within the same clock domain. The designed FIFO resulted in an area of 41.401 mm2, a power dissipation of 0.506 mW and a critical path delay of 0.03 ps when a 15 nm open-cell library from Nangate was used. The design is also implemented using an Arria II field programmable gate array (FPGA), which results in a maximum clock frequency of 33.33 GHz. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:Sustainability in in-vehicle communication comprises the integration of wireless technology for faster and more reliable connectivity. Driverless vehicles need to schedule various tasks on a priority basis. The first-in-first-out (FIFO) data structure is critical for handling sensor data and communication information, and a memory queue is important for controlling data flow through organized read and write processes. This study focuses on the design, verification and synthesis of a FIFO with a size of 4k bytes. By operating on a single clock signal, synchronous FIFO enables smooth data transmission between a source and destination within the same clock domain. The designed FIFO resulted in an area of 41.401 mm2, a power dissipation of 0.506 mW and a critical path delay of 0.03 ps when a 15 nm open-cell library from Nangate was used. The design is also implemented using an Arria II field programmable gate array (FPGA), which results in a maximum clock frequency of 33.33 GHz. [ABSTRACT FROM AUTHOR]
ISSN:02181266
DOI:10.1142/S0218126625503232