Design, Verification and Hardware Implementation of 4kB Synchronous FIFO for Automatic Vehicle Communication Applications.
Saved in:
| Title: | Design, Verification and Hardware Implementation of 4kB Synchronous FIFO for Automatic Vehicle Communication Applications. |
|---|---|
| Authors: | Mathew, Ribu1 (AUTHOR) ribu.mathew@gmail.com, Maila, Madhushankara1 (AUTHOR) madhushankar.m@manipal.edu, Kulai, Trishal1 (AUTHOR) trishal.msismpl2023@learner.manipal.edu |
| Source: | Journal of Circuits, Systems & Computers. 8/1/2025, Vol. 34 Issue 12, p1-13. 13p. |
| Subjects: | Flow control (Data transmission systems), Integrated circuit verification, Data structures, First in, first out (Queuing theory), Statistical smoothing |
| Abstract: | Sustainability in in-vehicle communication comprises the integration of wireless technology for faster and more reliable connectivity. Driverless vehicles need to schedule various tasks on a priority basis. The first-in-first-out (FIFO) data structure is critical for handling sensor data and communication information, and a memory queue is important for controlling data flow through organized read and write processes. This study focuses on the design, verification and synthesis of a FIFO with a size of 4k bytes. By operating on a single clock signal, synchronous FIFO enables smooth data transmission between a source and destination within the same clock domain. The designed FIFO resulted in an area of 41.401 mm2, a power dissipation of 0.506 mW and a critical path delay of 0.03 ps when a 15 nm open-cell library from Nangate was used. The design is also implemented using an Arria II field programmable gate array (FPGA), which results in a maximum clock frequency of 33.33 GHz. [ABSTRACT FROM AUTHOR] |
| Copyright of Journal of Circuits, Systems & Computers is the property of World Scientific Publishing Company and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
|---|---|
| Header | DbId: egs DbLabel: Engineering Source An: 186017924 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
| IllustrationInfo | |
| Items | – Name: Title Label: Title Group: Ti Data: Design, Verification and Hardware Implementation of 4kB Synchronous FIFO for Automatic Vehicle Communication Applications. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Mathew%2C+Ribu%22">Mathew, Ribu</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> ribu.mathew@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Maila%2C+Madhushankara%22">Maila, Madhushankara</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> madhushankar.m@manipal.edu</i><br /><searchLink fieldCode="AR" term="%22Kulai%2C+Trishal%22">Kulai, Trishal</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> trishal.msismpl2023@learner.manipal.edu</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Journal+of+Circuits%2C+Systems+%26+Computers%22">Journal of Circuits, Systems & Computers</searchLink>. 8/1/2025, Vol. 34 Issue 12, p1-13. 13p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Flow+control+%28Data+transmission+systems%29%22">Flow control (Data transmission systems)</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuit+verification%22">Integrated circuit verification</searchLink><br /><searchLink fieldCode="DE" term="%22Data+structures%22">Data structures</searchLink><br /><searchLink fieldCode="DE" term="%22First+in%2C+first+out+%28Queuing+theory%29%22">First in, first out (Queuing theory)</searchLink><br /><searchLink fieldCode="DE" term="%22Statistical+smoothing%22">Statistical smoothing</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Sustainability in in-vehicle communication comprises the integration of wireless technology for faster and more reliable connectivity. Driverless vehicles need to schedule various tasks on a priority basis. The first-in-first-out (FIFO) data structure is critical for handling sensor data and communication information, and a memory queue is important for controlling data flow through organized read and write processes. This study focuses on the design, verification and synthesis of a FIFO with a size of 4k bytes. By operating on a single clock signal, synchronous FIFO enables smooth data transmission between a source and destination within the same clock domain. The designed FIFO resulted in an area of 41.401 mm2, a power dissipation of 0.506 mW and a critical path delay of 0.03 ps when a 15 nm open-cell library from Nangate was used. The design is also implemented using an Arria II field programmable gate array (FPGA), which results in a maximum clock frequency of 33.33 GHz. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Journal of Circuits, Systems & Computers is the property of World Scientific Publishing Company and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=186017924 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1142/S0218126625503232 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 13 StartPage: 1 Subjects: – SubjectFull: Flow control (Data transmission systems) Type: general – SubjectFull: Integrated circuit verification Type: general – SubjectFull: Data structures Type: general – SubjectFull: First in, first out (Queuing theory) Type: general – SubjectFull: Statistical smoothing Type: general Titles: – TitleFull: Design, Verification and Hardware Implementation of 4kB Synchronous FIFO for Automatic Vehicle Communication Applications. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Mathew, Ribu – PersonEntity: Name: NameFull: Maila, Madhushankara – PersonEntity: Name: NameFull: Kulai, Trishal IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 08 Text: 8/1/2025 Type: published Y: 2025 Identifiers: – Type: issn-print Value: 02181266 Numbering: – Type: volume Value: 34 – Type: issue Value: 12 Titles: – TitleFull: Journal of Circuits, Systems & Computers Type: main |
| ResultId | 1 |
