APA (7th ed.) Citation

Ambekar, V., Theja, A., Panchore, M., Rajan, C., & Neole, B. (2025). Investigation of ITC Impact on Negative Bias HJVTFET for Implementing Universal Logic Gates. International Journal of Numerical Modelling, 38(3), 1. https://doi.org/10.1002/jnm.70057

Chicago Style (17th ed.) Citation

Ambekar, Vikas, A. Theja, Meena Panchore, Chithraja Rajan, and Bhumika Neole. "Investigation of ITC Impact on Negative Bias HJVTFET for Implementing Universal Logic Gates." International Journal of Numerical Modelling 38, no. 3 (2025): 1. https://doi.org/10.1002/jnm.70057.

MLA (9th ed.) Citation

Ambekar, Vikas, et al. "Investigation of ITC Impact on Negative Bias HJVTFET for Implementing Universal Logic Gates." International Journal of Numerical Modelling, vol. 38, no. 3, 2025, p. 1, https://doi.org/10.1002/jnm.70057.