Investigation of ITC Impact on Negative Bias HJVTFET for Implementing Universal Logic Gates.
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| Title: | Investigation of ITC Impact on Negative Bias HJVTFET for Implementing Universal Logic Gates. |
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| Authors: | Ambekar, Vikas1 (AUTHOR) vikasa.phd20.ec@nitp.ac.in, Theja, A.1 (AUTHOR), Panchore, Meena1 (AUTHOR), Rajan, Chithraja2 (AUTHOR), Neole, Bhumika3 (AUTHOR) |
| Source: | International Journal of Numerical Modelling. May/Jun2025, Vol. 38 Issue 3, p1-13. 13p. |
| Subjects: | Computer logic, Mathematical logic, NAND gates, Boolean functions, Choice (Psychology) |
| Abstract: | The objective of this study is to examine how interface trap charges (ITC) influence the logic performance of a p‐type heterojunction vertical TFET structure without and with gate overlap (HJVTFET‐WOG and HJVTFET‐WG). The logic gates can be realized with the help of the HJ‐VTFET that uses germanium as the source material. Using HJVTFET‐WOG and HJVTFET‐WG structures, our simulations have proven that two‐input universal logic functions like NAND and NOR gates may be realized. By adjusting the gate‐source overlap region and choosing the right silicon body thickness, the suggested vertical TFET is able to perform logic operations. For verifying the universal gate functionality, the HJVTFET drain current characteristic and energy band diagram are analyzed by considering the effect of trapped charges. The tunneling width of logic functions is narrower when the ITC is positive and wider when it is negative, and the effective sub‐threshold slopes (SS) have been examined. It has been discovered that positive ITCs can enhance device capabilities, while negative ITCs lead to diminishing functionality. The suggested HJVTFET‐WOG structure is a promising structure for implementing the logic gates for digital application under the influence of interface trap charges because its electrical performance is less vulnerable to ITC than HJVTFET‐WG. [ABSTRACT FROM AUTHOR] |
| Copyright of International Journal of Numerical Modelling is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 186112800 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Investigation of ITC Impact on Negative Bias HJVTFET for Implementing Universal Logic Gates. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Ambekar%2C+Vikas%22">Ambekar, Vikas</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> vikasa.phd20.ec@nitp.ac.in</i><br /><searchLink fieldCode="AR" term="%22Theja%2C+A%2E%22">Theja, A.</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Panchore%2C+Meena%22">Panchore, Meena</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Rajan%2C+Chithraja%22">Rajan, Chithraja</searchLink><relatesTo>2</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Neole%2C+Bhumika%22">Neole, Bhumika</searchLink><relatesTo>3</relatesTo> (AUTHOR) – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22International+Journal+of+Numerical+Modelling%22">International Journal of Numerical Modelling</searchLink>. May/Jun2025, Vol. 38 Issue 3, p1-13. 13p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Computer+logic%22">Computer logic</searchLink><br /><searchLink fieldCode="DE" term="%22Mathematical+logic%22">Mathematical logic</searchLink><br /><searchLink fieldCode="DE" term="%22NAND+gates%22">NAND gates</searchLink><br /><searchLink fieldCode="DE" term="%22Boolean+functions%22">Boolean functions</searchLink><br /><searchLink fieldCode="DE" term="%22Choice+%28Psychology%29%22">Choice (Psychology)</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: The objective of this study is to examine how interface trap charges (ITC) influence the logic performance of a p‐type heterojunction vertical TFET structure without and with gate overlap (HJVTFET‐WOG and HJVTFET‐WG). The logic gates can be realized with the help of the HJ‐VTFET that uses germanium as the source material. Using HJVTFET‐WOG and HJVTFET‐WG structures, our simulations have proven that two‐input universal logic functions like NAND and NOR gates may be realized. By adjusting the gate‐source overlap region and choosing the right silicon body thickness, the suggested vertical TFET is able to perform logic operations. For verifying the universal gate functionality, the HJVTFET drain current characteristic and energy band diagram are analyzed by considering the effect of trapped charges. The tunneling width of logic functions is narrower when the ITC is positive and wider when it is negative, and the effective sub‐threshold slopes (SS) have been examined. It has been discovered that positive ITCs can enhance device capabilities, while negative ITCs lead to diminishing functionality. The suggested HJVTFET‐WOG structure is a promising structure for implementing the logic gates for digital application under the influence of interface trap charges because its electrical performance is less vulnerable to ITC than HJVTFET‐WG. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of International Journal of Numerical Modelling is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1002/jnm.70057 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 13 StartPage: 1 Subjects: – SubjectFull: Computer logic Type: general – SubjectFull: Mathematical logic Type: general – SubjectFull: NAND gates Type: general – SubjectFull: Boolean functions Type: general – SubjectFull: Choice (Psychology) Type: general Titles: – TitleFull: Investigation of ITC Impact on Negative Bias HJVTFET for Implementing Universal Logic Gates. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Ambekar, Vikas – PersonEntity: Name: NameFull: Theja, A. – PersonEntity: Name: NameFull: Panchore, Meena – PersonEntity: Name: NameFull: Rajan, Chithraja – PersonEntity: Name: NameFull: Neole, Bhumika IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 05 Text: May/Jun2025 Type: published Y: 2025 Identifiers: – Type: issn-print Value: 08943370 Numbering: – Type: volume Value: 38 – Type: issue Value: 3 Titles: – TitleFull: International Journal of Numerical Modelling Type: main |
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