8T-SRAM Computing-in-Memory Macro with Bitline Leakage Compensation.
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| Title: | 8T-SRAM Computing-in-Memory Macro with Bitline Leakage Compensation. |
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| Authors: | Peng, Chunyu1,2 (AUTHOR) cyupeng@ahu.edu.cn, Chen, Junbo1,2 (AUTHOR) wb23201010@stu.ahu.edu.cn, Zhao, Mengyi1,2 (AUTHOR) 2495363782@qq.com, Lu, Wenjuan1,2 (AUTHOR) wjlu@ahu.edu.cn, Lin, Zhiting1,2 (AUTHOR) ztlin@ahu.edu.cn, Hao, Licai1,2 (AUTHOR) 21145@ahu.edu.cn, Li, Xin1,2 (AUTHOR) lixin@ahu.edu.cn, Dai, Chenghu1,2 (AUTHOR) daichenghu@ahu.edu.cn, Wu, Xiulong1,2 (AUTHOR) xiulong@ahu.edu.cn |
| Source: | Circuits, Systems & Signal Processing. Jul2025, Vol. 44 Issue 7, p4607-4625. 19p. |
| Subjects: | Associative storage, Stray currents, Artificial intelligence, Complementary metal oxide semiconductors, Computers |
| Abstract: | Computing-in-memory (CIM) technology has been developed to improve computer hardware efficiency for intelligent big data applications. An 8T-SRAM CIM macro with bitline leakage compensation ability is proposed in this study. In SRAM read mode, the proposed circuit solves the problem of read failure caused by bitline leakage current. In the write operation, the proposed circuit writes through the double-wordline, which can effectively improve the write static noise margin (WSNM) of the bitcell and reduce its write delay. When performing XNOR-and-accumulation (XAC) operations, the proposed circuit can effectively compensate the offset of the accumulated results due to bitline leakage current, thereby reducing output errors. In addition, this circuit can also be configured as binary content-addressable memory (BCAM) mode, and leakage compensation can be performed in this mode. A logic-AND sense amplifier (LASA) structure is also proposed, which can be applied in the SRAM read and BCAM modes. The proposed circuit is simulated in 55 nm CMOS process, under 1.2 V supply voltage. The proposed system demonstrates an energy efficiency of 62.7 TOPS/W, and effectively improves the anti-leakage ability of the array in all three modes. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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| Abstract: | Computing-in-memory (CIM) technology has been developed to improve computer hardware efficiency for intelligent big data applications. An 8T-SRAM CIM macro with bitline leakage compensation ability is proposed in this study. In SRAM read mode, the proposed circuit solves the problem of read failure caused by bitline leakage current. In the write operation, the proposed circuit writes through the double-wordline, which can effectively improve the write static noise margin (WSNM) of the bitcell and reduce its write delay. When performing XNOR-and-accumulation (XAC) operations, the proposed circuit can effectively compensate the offset of the accumulated results due to bitline leakage current, thereby reducing output errors. In addition, this circuit can also be configured as binary content-addressable memory (BCAM) mode, and leakage compensation can be performed in this mode. A logic-AND sense amplifier (LASA) structure is also proposed, which can be applied in the SRAM read and BCAM modes. The proposed circuit is simulated in 55 nm CMOS process, under 1.2 V supply voltage. The proposed system demonstrates an energy efficiency of 62.7 TOPS/W, and effectively improves the anti-leakage ability of the array in all three modes. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 0278081X |
| DOI: | 10.1007/s00034-025-03052-6 |
