Effect of Hetero-Dielectric Gate on Direct Current, Radio Frequency/Analog, and Linearity Performance of Dual-Source Vertical Tunnel Field Effect Transistor for Low-Power Applications.
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| Title: | Effect of Hetero-Dielectric Gate on Direct Current, Radio Frequency/Analog, and Linearity Performance of Dual-Source Vertical Tunnel Field Effect Transistor for Low-Power Applications. |
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| Authors: | Singh, Sheetal1 (AUTHOR) sheetalsinghaug29@gmail.com, Wairya, Subodh1 (AUTHOR) |
| Source: | Semiconductors. Jul2025, Vol. 59 Issue 7, p650-660. 11p. |
| Subjects: | Field-effect transistors, Intermodulation distortion, Stray currents, Radio frequency, Dielectrics |
| Abstract: | The novel hetero-dielectric gate dual-source vertical tunnel field effect transistor architecture (HDG-DS-VTFET) is investigated in this paper along with an analysis of its DC, RF/Analog, noise, and linearity characteristics. This device features a vertically stacked gate oxide structure of HfO2/SiO2 in a dual-source vertical TFET configuration that reflects enhanced ION and better leakage current suppression compared to High-k-dielectric (HfO2)-DS-VTFET. Additionally, in comparison to HfO2-DS-VTFET, the HDG-DS-VTFET showed a reduced threshold voltage () of 0.21 V, a lower sub-threshold value of 8.5 mV/decade, and a higher ION/IOFF reflected as 7.1 × 1012. The present work used a calibrated SILVACO technology computer-aided design (TCAD) simulator. The proposed device has been thoroughly examined concerning its RF/Analog performance parameters, such as gate capacitances, gain-bandwidth product (GBP), cut-off frequency (), early voltage, intrinsic gain, and compared to a high-k dielectric (HfO2) DS-VTFET structure. Furthermore, a linearity analysis was performed as a figure of merit (FOM), considering several parameters such as the 1-db compression point, the 3rd-order intermodulation intercept point (IIP3), the 3rd-order voltage intercepts point (VIP3), and the 3rd-order intermodulation distortion point (IMD3). In comparison to the high-k dielectric (HfO2) DS-VTFET, the proposed HDG-DS-VTFET showed a significantly reduced sub threshold value of approximately 77% which gives a notably high ON current with low () for possible low-power linear and RF applications. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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| Abstract: | The novel hetero-dielectric gate dual-source vertical tunnel field effect transistor architecture (HDG-DS-VTFET) is investigated in this paper along with an analysis of its DC, RF/Analog, noise, and linearity characteristics. This device features a vertically stacked gate oxide structure of HfO2/SiO2 in a dual-source vertical TFET configuration that reflects enhanced ION and better leakage current suppression compared to High-k-dielectric (HfO2)-DS-VTFET. Additionally, in comparison to HfO2-DS-VTFET, the HDG-DS-VTFET showed a reduced threshold voltage () of 0.21 V, a lower sub-threshold value of 8.5 mV/decade, and a higher ION/IOFF reflected as 7.1 × 1012. The present work used a calibrated SILVACO technology computer-aided design (TCAD) simulator. The proposed device has been thoroughly examined concerning its RF/Analog performance parameters, such as gate capacitances, gain-bandwidth product (GBP), cut-off frequency (), early voltage, intrinsic gain, and compared to a high-k dielectric (HfO2) DS-VTFET structure. Furthermore, a linearity analysis was performed as a figure of merit (FOM), considering several parameters such as the 1-db compression point, the 3rd-order intermodulation intercept point (IIP3), the 3rd-order voltage intercepts point (VIP3), and the 3rd-order intermodulation distortion point (IMD3). In comparison to the high-k dielectric (HfO2) DS-VTFET, the proposed HDG-DS-VTFET showed a significantly reduced sub threshold value of approximately 77% which gives a notably high ON current with low () for possible low-power linear and RF applications. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 10637826 |
| DOI: | 10.1134/S1063782625600664 |
