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Compact design of universal gates with non-aligned gate technology and assessment of its performance in a TCAD Environment.

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Title: Compact design of universal gates with non-aligned gate technology and assessment of its performance in a TCAD Environment.
Authors: Sangam, Sri Lakshmi1 (AUTHOR), Sinha, Arun Kumar1 (AUTHOR) arunkumar.s@vitap.ac.in
Source: International Journal of Electronics. Sep2025, Vol. 112 Issue 9, p1860-1874. 15p.
Subjects: NAND gates, Computer-aided design, Scalability, Electronic circuit design, Logic circuits, Computer performance
Abstract: This paper proposes a technology computer-aided design (TCAD) of a compact single-device NAND and NOR logic gates in 215 nm device length along with speed and power performance results. The universal gates are designed with non-aligned double gate technology, and this helps to reduce the transistor count, giving a compact design structure. The static characteristics and input pattern sensitivity of the NAND and NOR structures are investigated in this work. By using graphical method, the optimal supply voltage of the universal gates was determined. The optimal supply voltage of the NAND gate and NOR gate was 0.9 V and 0.84 V, respectively, at an input frequency of 1 GHz. Further, the device scalability of the proposed structures was analysed. When compared to the past work, the proposed NAND gate and NOR gate improves delay performance by 25.02% and 35.63%, respectively. Additionally, a reduction of 10% and 16% in its supply voltage is achieved. Therefore, the proposed gate has potential to operate at higher frequency with reduced supply voltage, making them suitable in circuit applications. [ABSTRACT FROM AUTHOR]
Copyright of International Journal of Electronics is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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DbLabel: Engineering Source
An: 187098015
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
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  Data: Compact design of universal gates with non-aligned gate technology and assessment of its performance in a TCAD Environment.
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  Data: <searchLink fieldCode="AR" term="%22Sangam%2C+Sri+Lakshmi%22">Sangam, Sri Lakshmi</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Sinha%2C+Arun+Kumar%22">Sinha, Arun Kumar</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> arunkumar.s@vitap.ac.in</i>
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  Data: <searchLink fieldCode="JN" term="%22International+Journal+of+Electronics%22">International Journal of Electronics</searchLink>. Sep2025, Vol. 112 Issue 9, p1860-1874. 15p.
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  Data: <searchLink fieldCode="DE" term="%22NAND+gates%22">NAND gates</searchLink><br /><searchLink fieldCode="DE" term="%22Computer-aided+design%22">Computer-aided design</searchLink><br /><searchLink fieldCode="DE" term="%22Scalability%22">Scalability</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+circuit+design%22">Electronic circuit design</searchLink><br /><searchLink fieldCode="DE" term="%22Logic+circuits%22">Logic circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+performance%22">Computer performance</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: This paper proposes a technology computer-aided design (TCAD) of a compact single-device NAND and NOR logic gates in 215 nm device length along with speed and power performance results. The universal gates are designed with non-aligned double gate technology, and this helps to reduce the transistor count, giving a compact design structure. The static characteristics and input pattern sensitivity of the NAND and NOR structures are investigated in this work. By using graphical method, the optimal supply voltage of the universal gates was determined. The optimal supply voltage of the NAND gate and NOR gate was 0.9 V and 0.84 V, respectively, at an input frequency of 1 GHz. Further, the device scalability of the proposed structures was analysed. When compared to the past work, the proposed NAND gate and NOR gate improves delay performance by 25.02% and 35.63%, respectively. Additionally, a reduction of 10% and 16% in its supply voltage is achieved. Therefore, the proposed gate has potential to operate at higher frequency with reduced supply voltage, making them suitable in circuit applications. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of International Journal of Electronics is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1080/00207217.2024.2408790
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      – Code: eng
        Text: English
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        PageCount: 15
        StartPage: 1860
    Subjects:
      – SubjectFull: NAND gates
        Type: general
      – SubjectFull: Computer-aided design
        Type: general
      – SubjectFull: Scalability
        Type: general
      – SubjectFull: Electronic circuit design
        Type: general
      – SubjectFull: Logic circuits
        Type: general
      – SubjectFull: Computer performance
        Type: general
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              M: 09
              Text: Sep2025
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              Y: 2025
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