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Thin dielectric to dielectric hydrophilic wafer bonding for FD-SOI and C-FET manufacturing.

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Title: Thin dielectric to dielectric hydrophilic wafer bonding for FD-SOI and C-FET manufacturing.
Authors: Noel, P.1 (AUTHOR) paul.noel@cea.fr, Larrey, V.1 (AUTHOR), Tardif, S.2 (AUTHOR), Rieutord, F.3 (AUTHOR), Landru, D.3 (AUTHOR), Fournel, F.1 (AUTHOR)
Source: Solid-State Electronics. Nov2025, Vol. 229, pN.PAG-N.PAG. 1p.
Subjects: Interfacial bonding, Dielectrics, Silicon-on-insulator technology, Semiconductor wafer bonding, Field-effect transistors, Nanoparticles
Abstract: • Direct bonding involving thin symmetrical dielectric layers may be used for silicon layer transfer for FD-SOI and C-FET technologies. • Scanning Acoustic Microscopy characterization of bonded wafers within thin symmetric dielectric layer. • Hard X-Ray Reflectometry @ ESRF characterization of bonding interface and formation of interfacial nanoclusters is evidenced. • Bonding interface toughness for high transfer quality has been assessed. Direct hydrophilic bonding of silicon structures with low dielectric thickness may lead to the generation of bonding voids during annealing. Yet, silicon layer transfer requires thinner dielectric layers for FD–SOI and C-FET advanced devices. The aim being high bond strengths and low bonding void densities for advanced technological nodes, we show the crucial impact of bonding layer properties on interface sealing and bonding energies. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:• Direct bonding involving thin symmetrical dielectric layers may be used for silicon layer transfer for FD-SOI and C-FET technologies. • Scanning Acoustic Microscopy characterization of bonded wafers within thin symmetric dielectric layer. • Hard X-Ray Reflectometry @ ESRF characterization of bonding interface and formation of interfacial nanoclusters is evidenced. • Bonding interface toughness for high transfer quality has been assessed. Direct hydrophilic bonding of silicon structures with low dielectric thickness may lead to the generation of bonding voids during annealing. Yet, silicon layer transfer requires thinner dielectric layers for FD–SOI and C-FET advanced devices. The aim being high bond strengths and low bonding void densities for advanced technological nodes, we show the crucial impact of bonding layer properties on interface sealing and bonding energies. [ABSTRACT FROM AUTHOR]
ISSN:00381101
DOI:10.1016/j.sse.2025.109188