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Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories Through Optimal Design of BCH Codes.

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Bibliographic Details
Title: Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories Through Optimal Design of BCH Codes.
Authors: Nabipour, Saeideh1 (AUTHOR) nabipour@uni-bremen.de, Javidan, Javad2 (AUTHOR) javidan@uma.ac.ir
Source: Journal of Circuits, Systems & Computers. 11/30/2025, Vol. 34 Issue 17, p1-25. 25p.
Subjects: Computer hardware description languages, Error-correcting codes, Data warehousing, Parallel processing, Transistors
Abstract: The size reduction of transistors in the latest flash memory generation has resulted in programming and data erasure issues within these designs. Consequently, ensuring reliable data storage has become a significant challenge for these memory structures. To tackle this challenge, error-correcting codes like Bose–Chaudhuri–Hocquenghem (BCH) codes are employed in the controllers of these memories. When decoding BCH codes, two crucial factors are the delay in error correction and the hardware requirements of each sub-block. This paper proposes an effective solution to enhance error correction speed and optimize the decoder circuit's efficiency. It suggests implementing a parallel architecture for the BCH decoder's sub-blocks and a three-stage pipeline is also adopted in our decoder to increase the throughput. Moreover, to reduce the hardware requirements of the BCH decoder block, an algorithm based on XOR sharing is introduced to eliminate redundant gates in the search Chien block. The proposed decoder is simulated using the VHDL hardware description language and subsequently synthesized with Xilinx ISE software. When compared to the other similar BCH decoder blocks currently available, the suggested decoder reduces area complexity by 50% for BCH (279, 256, 3) and significantly reduces error correction time to 4.1 ns. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:The size reduction of transistors in the latest flash memory generation has resulted in programming and data erasure issues within these designs. Consequently, ensuring reliable data storage has become a significant challenge for these memory structures. To tackle this challenge, error-correcting codes like Bose–Chaudhuri–Hocquenghem (BCH) codes are employed in the controllers of these memories. When decoding BCH codes, two crucial factors are the delay in error correction and the hardware requirements of each sub-block. This paper proposes an effective solution to enhance error correction speed and optimize the decoder circuit's efficiency. It suggests implementing a parallel architecture for the BCH decoder's sub-blocks and a three-stage pipeline is also adopted in our decoder to increase the throughput. Moreover, to reduce the hardware requirements of the BCH decoder block, an algorithm based on XOR sharing is introduced to eliminate redundant gates in the search Chien block. The proposed decoder is simulated using the VHDL hardware description language and subsequently synthesized with Xilinx ISE software. When compared to the other similar BCH decoder blocks currently available, the suggested decoder reduces area complexity by 50% for BCH (279, 256, 3) and significantly reduces error correction time to 4.1 ns. [ABSTRACT FROM AUTHOR]
ISSN:02181266
DOI:10.1142/S0218126624502256