View in EDS

Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories Through Optimal Design of BCH Codes.

Saved in:
Bibliographic Details
Title: Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories Through Optimal Design of BCH Codes.
Authors: Nabipour, Saeideh1 (AUTHOR) nabipour@uni-bremen.de, Javidan, Javad2 (AUTHOR) javidan@uma.ac.ir
Source: Journal of Circuits, Systems & Computers. 11/30/2025, Vol. 34 Issue 17, p1-25. 25p.
Subjects: Computer hardware description languages, Error-correcting codes, Data warehousing, Parallel processing, Transistors
Abstract: The size reduction of transistors in the latest flash memory generation has resulted in programming and data erasure issues within these designs. Consequently, ensuring reliable data storage has become a significant challenge for these memory structures. To tackle this challenge, error-correcting codes like Bose–Chaudhuri–Hocquenghem (BCH) codes are employed in the controllers of these memories. When decoding BCH codes, two crucial factors are the delay in error correction and the hardware requirements of each sub-block. This paper proposes an effective solution to enhance error correction speed and optimize the decoder circuit's efficiency. It suggests implementing a parallel architecture for the BCH decoder's sub-blocks and a three-stage pipeline is also adopted in our decoder to increase the throughput. Moreover, to reduce the hardware requirements of the BCH decoder block, an algorithm based on XOR sharing is introduced to eliminate redundant gates in the search Chien block. The proposed decoder is simulated using the VHDL hardware description language and subsequently synthesized with Xilinx ISE software. When compared to the other similar BCH decoder blocks currently available, the suggested decoder reduces area complexity by 50% for BCH (279, 256, 3) and significantly reduces error correction time to 4.1 ns. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Circuits, Systems & Computers is the property of World Scientific Publishing Company and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
FullText Text:
  Availability: 0
Header DbId: egs
DbLabel: Engineering Source
An: 188123475
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories Through Optimal Design of BCH Codes.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Nabipour%2C+Saeideh%22">Nabipour, Saeideh</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> nabipour@uni-bremen.de</i><br /><searchLink fieldCode="AR" term="%22Javidan%2C+Javad%22">Javidan, Javad</searchLink><relatesTo>2</relatesTo> (AUTHOR)<i> javidan@uma.ac.ir</i>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Journal+of+Circuits%2C+Systems+%26+Computers%22">Journal of Circuits, Systems & Computers</searchLink>. 11/30/2025, Vol. 34 Issue 17, p1-25. 25p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Computer+hardware+description+languages%22">Computer hardware description languages</searchLink><br /><searchLink fieldCode="DE" term="%22Error-correcting+codes%22">Error-correcting codes</searchLink><br /><searchLink fieldCode="DE" term="%22Data+warehousing%22">Data warehousing</searchLink><br /><searchLink fieldCode="DE" term="%22Parallel+processing%22">Parallel processing</searchLink><br /><searchLink fieldCode="DE" term="%22Transistors%22">Transistors</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: The size reduction of transistors in the latest flash memory generation has resulted in programming and data erasure issues within these designs. Consequently, ensuring reliable data storage has become a significant challenge for these memory structures. To tackle this challenge, error-correcting codes like Bose–Chaudhuri–Hocquenghem (BCH) codes are employed in the controllers of these memories. When decoding BCH codes, two crucial factors are the delay in error correction and the hardware requirements of each sub-block. This paper proposes an effective solution to enhance error correction speed and optimize the decoder circuit's efficiency. It suggests implementing a parallel architecture for the BCH decoder's sub-blocks and a three-stage pipeline is also adopted in our decoder to increase the throughput. Moreover, to reduce the hardware requirements of the BCH decoder block, an algorithm based on XOR sharing is introduced to eliminate redundant gates in the search Chien block. The proposed decoder is simulated using the VHDL hardware description language and subsequently synthesized with Xilinx ISE software. When compared to the other similar BCH decoder blocks currently available, the suggested decoder reduces area complexity by 50% for BCH (279, 256, 3) and significantly reduces error correction time to 4.1 ns. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Journal of Circuits, Systems & Computers is the property of World Scientific Publishing Company and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=188123475
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1142/S0218126624502256
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 25
        StartPage: 1
    Subjects:
      – SubjectFull: Computer hardware description languages
        Type: general
      – SubjectFull: Error-correcting codes
        Type: general
      – SubjectFull: Data warehousing
        Type: general
      – SubjectFull: Parallel processing
        Type: general
      – SubjectFull: Transistors
        Type: general
    Titles:
      – TitleFull: Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories Through Optimal Design of BCH Codes.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Nabipour, Saeideh
      – PersonEntity:
          Name:
            NameFull: Javidan, Javad
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 30
              M: 11
              Text: 11/30/2025
              Type: published
              Y: 2025
          Identifiers:
            – Type: issn-print
              Value: 02181266
          Numbering:
            – Type: volume
              Value: 34
            – Type: issue
              Value: 17
          Titles:
            – TitleFull: Journal of Circuits, Systems & Computers
              Type: main
ResultId 1