View in EDS PDF Full Text

Research on Retimer structure and key technologies for Chiplet interconnection.

Saved in:
Bibliographic Details
Title: Research on Retimer structure and key technologies for Chiplet interconnection.
Authors: SUN, Yubo1 sunofficial9527@outlook.com, ZHOU, Hongwei2,3 zhouhongwei@nudt.edu.cn, SUN, Xingyu2,3, HE, Xingyang2,3 sozzler@163.com, SONG, Zhaoyang2,3 songzhaoyang@nudt.edu.cn, CHEN, Zhiqiang2,3 czq20@nudt.edu.cn
Source: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Aug2025, Vol. 47 Issue 8, p1381-1390. 10p.
Subjects: Architectural details, Interface circuits, Credit management, Value engineering, Computer systems
Abstract: Connecting multiple dies through Chiplet interconnect interfaces has become the mainstream of chip design in the post-Moore era. The Chiplet interconnection interface circuit is only used for interconnection of multiple Chiplets within a single package, with an extremely short transmission distance. In large-scale computing systems, multiple chips need to build larger-scale computing nodes. How to achieve long-distance interconnection of Chiplets in multiple chips at the board-level has become a very important issue. Intel and others have defined a Retimer for Chiplet interconnection interfaces in the universal Chiplet interconnect (UCIe) specification, but the architectural details are not disclosed. The research on Retimer for Chiplet interconnection interfaces in China is still blank. Combining with the formulation of the independent Chiplet interconnection interface standard, this paper proposes a Retimer (D2C_;Retimer) architecture for Chiplet interconnection to chip interconnection, which supports the conversion of the die-to-die (D2D) interface into a chip-to-chip (C2C) interface, realizing the interconnection of Chiplets across chips at the board level. Through key technologies such as the reliable transmission mechanism of Retimer, the credit mechanism of Retimer, and the hierarchical sideband transmission link, it not only achieves compatibility with the independent Chiplet interconnection standard, but also has advantages in credit management, reliable transmission, etc. Experiments show that the implemented Retimer can realize long-distance interconnection across packages between Chiplets without changing the existing independent interconnection standard, which is of great reference significance and engineering implementation value for improving the domestic Chiplet interconnection ecosystem. [ABSTRACT FROM AUTHOR]
Copyright of Computer Engineering & Science / Jisuanji Gongcheng yu Kexue is the property of Computer Engineering & Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
FullText Links:
  – Type: pdflink
Text:
  Availability: 0
Header DbId: egs
DbLabel: Engineering Source
An: 188160254
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: Research on Retimer structure and key technologies for Chiplet interconnection.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22SUN%2C+Yubo%22">SUN, Yubo</searchLink><relatesTo>1</relatesTo><i> sunofficial9527@outlook.com</i><br /><searchLink fieldCode="AR" term="%22ZHOU%2C+Hongwei%22">ZHOU, Hongwei</searchLink><relatesTo>2,3</relatesTo><i> zhouhongwei@nudt.edu.cn</i><br /><searchLink fieldCode="AR" term="%22SUN%2C+Xingyu%22">SUN, Xingyu</searchLink><relatesTo>2,3</relatesTo><br /><searchLink fieldCode="AR" term="%22HE%2C+Xingyang%22">HE, Xingyang</searchLink><relatesTo>2,3</relatesTo><i> sozzler@163.com</i><br /><searchLink fieldCode="AR" term="%22SONG%2C+Zhaoyang%22">SONG, Zhaoyang</searchLink><relatesTo>2,3</relatesTo><i> songzhaoyang@nudt.edu.cn</i><br /><searchLink fieldCode="AR" term="%22CHEN%2C+Zhiqiang%22">CHEN, Zhiqiang</searchLink><relatesTo>2,3</relatesTo><i> czq20@nudt.edu.cn</i>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Computer+Engineering+%26+Science+%2F+Jisuanji+Gongcheng+yu+Kexue%22">Computer Engineering & Science / Jisuanji Gongcheng yu Kexue</searchLink>. Aug2025, Vol. 47 Issue 8, p1381-1390. 10p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Architectural+details%22">Architectural details</searchLink><br /><searchLink fieldCode="DE" term="%22Interface+circuits%22">Interface circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Credit+management%22">Credit management</searchLink><br /><searchLink fieldCode="DE" term="%22Value+engineering%22">Value engineering</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+systems%22">Computer systems</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: Connecting multiple dies through Chiplet interconnect interfaces has become the mainstream of chip design in the post-Moore era. The Chiplet interconnection interface circuit is only used for interconnection of multiple Chiplets within a single package, with an extremely short transmission distance. In large-scale computing systems, multiple chips need to build larger-scale computing nodes. How to achieve long-distance interconnection of Chiplets in multiple chips at the board-level has become a very important issue. Intel and others have defined a Retimer for Chiplet interconnection interfaces in the universal Chiplet interconnect (UCIe) specification, but the architectural details are not disclosed. The research on Retimer for Chiplet interconnection interfaces in China is still blank. Combining with the formulation of the independent Chiplet interconnection interface standard, this paper proposes a Retimer (D2C_;Retimer) architecture for Chiplet interconnection to chip interconnection, which supports the conversion of the die-to-die (D2D) interface into a chip-to-chip (C2C) interface, realizing the interconnection of Chiplets across chips at the board level. Through key technologies such as the reliable transmission mechanism of Retimer, the credit mechanism of Retimer, and the hierarchical sideband transmission link, it not only achieves compatibility with the independent Chiplet interconnection standard, but also has advantages in credit management, reliable transmission, etc. Experiments show that the implemented Retimer can realize long-distance interconnection across packages between Chiplets without changing the existing independent interconnection standard, which is of great reference significance and engineering implementation value for improving the domestic Chiplet interconnection ecosystem. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Computer Engineering & Science / Jisuanji Gongcheng yu Kexue is the property of Computer Engineering & Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=188160254
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.3969/j.issn.1007-130X.2025.08.005
    Languages:
      – Code: chi
        Text: Chinese
    PhysicalDescription:
      Pagination:
        PageCount: 10
        StartPage: 1381
    Subjects:
      – SubjectFull: Architectural details
        Type: general
      – SubjectFull: Interface circuits
        Type: general
      – SubjectFull: Credit management
        Type: general
      – SubjectFull: Value engineering
        Type: general
      – SubjectFull: Computer systems
        Type: general
    Titles:
      – TitleFull: Research on Retimer structure and key technologies for Chiplet interconnection.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: SUN, Yubo
      – PersonEntity:
          Name:
            NameFull: ZHOU, Hongwei
      – PersonEntity:
          Name:
            NameFull: SUN, Xingyu
      – PersonEntity:
          Name:
            NameFull: HE, Xingyang
      – PersonEntity:
          Name:
            NameFull: SONG, Zhaoyang
      – PersonEntity:
          Name:
            NameFull: CHEN, Zhiqiang
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 08
              Text: Aug2025
              Type: published
              Y: 2025
          Identifiers:
            – Type: issn-print
              Value: 1007130X
          Numbering:
            – Type: volume
              Value: 47
            – Type: issue
              Value: 8
          Titles:
            – TitleFull: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue
              Type: main
ResultId 1