APA (7th ed.) Citation

Tirumalasetty, V. R., Babulu, K., & Naidu, G. A. (2025). A novel design of 1-bit full adders for eliminating voltage step in BBL-PT full adder using 32-nm CNTFET technology. International Journal of Electronics, 112(11), 2386. https://doi.org/10.1080/00207217.2025.2450735

Chicago Style (17th ed.) Citation

Tirumalasetty, Venkata Rao, K. Babulu, and G. Appala Naidu. "A Novel Design of 1-bit Full Adders for Eliminating Voltage Step in BBL-PT Full Adder Using 32-nm CNTFET Technology." International Journal of Electronics 112, no. 11 (2025): 2386. https://doi.org/10.1080/00207217.2025.2450735.

MLA (9th ed.) Citation

Tirumalasetty, Venkata Rao, et al. "A Novel Design of 1-bit Full Adders for Eliminating Voltage Step in BBL-PT Full Adder Using 32-nm CNTFET Technology." International Journal of Electronics, vol. 112, no. 11, 2025, p. 2386, https://doi.org/10.1080/00207217.2025.2450735.