Bibliographic Details
| Title: |
Design of 65 nm 6T SRAM using improved sense amplifiers and write driver circuits. |
| Authors: |
Truong, Quang Vinh1 tqvinh@hcmut.edu.vn, Tieu, Tuan Dat1 |
| Source: |
Majlesi Journal of Electrical Engineering. Sep2025, Issue 3, p1-11. 11p. |
| Subjects: |
Static random access memory, Electronic circuit design, Simulation methods & models, Nanostructured materials, Mathematical optimization, Line drivers (Integrated circuits), Electronic amplifiers |
| Abstract: |
Designing high-speed 6T SRAM for efficient read and write operations poses a significant challenge for circuit designers. In this paper, we propose a 65 nm 6T SRAM architecture using sense amplifiers and write driver circuits to enhance the read and write performance. The sense amplifier helps the reading process go faster and the reading data be more stable. The write driver is designed with a symmetrical structure to reduce the write delay. In addition, the control circuit performs the checking process to synchronize read operations, optimize latency without interruption. The simulation result shows that the read delay and write delay are 58.66 ps and 79.67 ps, respectively. These delays outperform most of the other study. [ABSTRACT FROM AUTHOR] |
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| Database: |
Engineering Source |
