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Design of 65 nm 6T SRAM using improved sense amplifiers and write driver circuits.

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Title: Design of 65 nm 6T SRAM using improved sense amplifiers and write driver circuits.
Authors: Truong, Quang Vinh1 tqvinh@hcmut.edu.vn, Tieu, Tuan Dat1
Source: Majlesi Journal of Electrical Engineering. Sep2025, Issue 3, p1-11. 11p.
Subjects: Static random access memory, Electronic circuit design, Simulation methods & models, Nanostructured materials, Mathematical optimization, Line drivers (Integrated circuits), Electronic amplifiers
Abstract: Designing high-speed 6T SRAM for efficient read and write operations poses a significant challenge for circuit designers. In this paper, we propose a 65 nm 6T SRAM architecture using sense amplifiers and write driver circuits to enhance the read and write performance. The sense amplifier helps the reading process go faster and the reading data be more stable. The write driver is designed with a symmetrical structure to reduce the write delay. In addition, the control circuit performs the checking process to synchronize read operations, optimize latency without interruption. The simulation result shows that the read delay and write delay are 58.66 ps and 79.67 ps, respectively. These delays outperform most of the other study. [ABSTRACT FROM AUTHOR]
Copyright of Majlesi Journal of Electrical Engineering is the property of OICC Press and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: Design of 65 nm 6T SRAM using improved sense amplifiers and write driver circuits.
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  Data: <searchLink fieldCode="AR" term="%22Truong%2C+Quang+Vinh%22">Truong, Quang Vinh</searchLink><relatesTo>1</relatesTo><i> tqvinh@hcmut.edu.vn</i><br /><searchLink fieldCode="AR" term="%22Tieu%2C+Tuan+Dat%22">Tieu, Tuan Dat</searchLink><relatesTo>1</relatesTo>
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  Data: <searchLink fieldCode="JN" term="%22Majlesi+Journal+of+Electrical+Engineering%22">Majlesi Journal of Electrical Engineering</searchLink>. Sep2025, Issue 3, p1-11. 11p.
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  Data: <searchLink fieldCode="DE" term="%22Static+random+access+memory%22">Static random access memory</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+circuit+design%22">Electronic circuit design</searchLink><br /><searchLink fieldCode="DE" term="%22Simulation+methods+%26+models%22">Simulation methods & models</searchLink><br /><searchLink fieldCode="DE" term="%22Nanostructured+materials%22">Nanostructured materials</searchLink><br /><searchLink fieldCode="DE" term="%22Mathematical+optimization%22">Mathematical optimization</searchLink><br /><searchLink fieldCode="DE" term="%22Line+drivers+%28Integrated+circuits%29%22">Line drivers (Integrated circuits)</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+amplifiers%22">Electronic amplifiers</searchLink>
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  Label: Abstract
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  Data: Designing high-speed 6T SRAM for efficient read and write operations poses a significant challenge for circuit designers. In this paper, we propose a 65 nm 6T SRAM architecture using sense amplifiers and write driver circuits to enhance the read and write performance. The sense amplifier helps the reading process go faster and the reading data be more stable. The write driver is designed with a symmetrical structure to reduce the write delay. In addition, the control circuit performs the checking process to synchronize read operations, optimize latency without interruption. The simulation result shows that the read delay and write delay are 58.66 ps and 79.67 ps, respectively. These delays outperform most of the other study. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Majlesi Journal of Electrical Engineering is the property of OICC Press and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
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      – Type: doi
        Value: 10.57647/j.mjee.2025.17413
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      – Code: eng
        Text: English
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        PageCount: 11
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    Subjects:
      – SubjectFull: Static random access memory
        Type: general
      – SubjectFull: Electronic circuit design
        Type: general
      – SubjectFull: Simulation methods & models
        Type: general
      – SubjectFull: Nanostructured materials
        Type: general
      – SubjectFull: Mathematical optimization
        Type: general
      – SubjectFull: Line drivers (Integrated circuits)
        Type: general
      – SubjectFull: Electronic amplifiers
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      – TitleFull: Design of 65 nm 6T SRAM using improved sense amplifiers and write driver circuits.
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            – D: 01
              M: 09
              Text: Sep2025
              Type: published
              Y: 2025
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