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Design of Floating-Point Adder Architecture with Multi-mode Capability.

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Title: Design of Floating-Point Adder Architecture with Multi-mode Capability.
Authors: Krishnan, Thiruvenkadam1 (AUTHOR) thiruvlsi@gmail.com, Subramanian, Saravanan2 (AUTHOR) saran.vpm@gmail.com, Anguraj, Parthibaraj3 (AUTHOR) parthi63raja@gmail.com
Source: Circuits, Systems & Signal Processing. Dec2025, Vol. 44 Issue 12, p9725-9738. 14p.
Subjects: Floating-point arithmetic, Application-specific integrated circuits, Real-time computing, Digital signal processing, Field programmable gate arrays
Abstract: Modern real-time applications, such as multimedia and digital signal processing, frequently require floating-point (FP) arithmetic. The currently available dual-mode fused FP three-term adder supports either a single double-precision (DP) addition or two parallel single-precision (SP) additions. However, it lacks support for quadruple-precision (QP) additions, resulting in inefficient area utilization when multi-precision computations are required. To overcome this limitation, this study introduces a multi-mode fused FP three-term adder capable of performing one QP addition, two parallel DP additions, or four parallel SP additions. The proposed design also provides robust support for exceptional cases, such as zero, NaN, and infinity, and handles both normal and subnormal operations. The architecture has been implemented and evaluated on both ASIC and FPGA platforms. By enabling efficient resource sharing across the three precision modes, the proposed multi-mode design achieves lower area usage compared to existing adders, including those tailored for individual QP, dual DP, and quad SP additions, as well as configurations combining one QP unit with two dual-mode adders. [ABSTRACT FROM AUTHOR]
Copyright of Circuits, Systems & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: Design of Floating-Point Adder Architecture with Multi-mode Capability.
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  Data: <searchLink fieldCode="DE" term="%22Floating-point+arithmetic%22">Floating-point arithmetic</searchLink><br /><searchLink fieldCode="DE" term="%22Application-specific+integrated+circuits%22">Application-specific integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Real-time+computing%22">Real-time computing</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+signal+processing%22">Digital signal processing</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink>
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  Data: Modern real-time applications, such as multimedia and digital signal processing, frequently require floating-point (FP) arithmetic. The currently available dual-mode fused FP three-term adder supports either a single double-precision (DP) addition or two parallel single-precision (SP) additions. However, it lacks support for quadruple-precision (QP) additions, resulting in inefficient area utilization when multi-precision computations are required. To overcome this limitation, this study introduces a multi-mode fused FP three-term adder capable of performing one QP addition, two parallel DP additions, or four parallel SP additions. The proposed design also provides robust support for exceptional cases, such as zero, NaN, and infinity, and handles both normal and subnormal operations. The architecture has been implemented and evaluated on both ASIC and FPGA platforms. By enabling efficient resource sharing across the three precision modes, the proposed multi-mode design achieves lower area usage compared to existing adders, including those tailored for individual QP, dual DP, and quad SP additions, as well as configurations combining one QP unit with two dual-mode adders. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of Circuits, Systems & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1007/s00034-025-03270-y
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      – Code: eng
        Text: English
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        PageCount: 14
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      – SubjectFull: Floating-point arithmetic
        Type: general
      – SubjectFull: Application-specific integrated circuits
        Type: general
      – SubjectFull: Real-time computing
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      – SubjectFull: Digital signal processing
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      – SubjectFull: Field programmable gate arrays
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              M: 12
              Text: Dec2025
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              Y: 2025
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