An efficient algorithmic framework to minimize the summand matrix in binary multiplication.
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| Title: | An efficient algorithmic framework to minimize the summand matrix in binary multiplication. |
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| Authors: | Verma, Amit1 (AUTHOR), Prateek, Manish2 (AUTHOR), Shivhare, Shiv Naresh3 (AUTHOR), Singh, Thipendra P.3 (AUTHOR), Kumar, Anuj4 (AUTHOR), Ranjan, Rakesh1 (AUTHOR), Priyadarshi, Rahul5 (AUTHOR) rahul.glorious91@gmail.com |
| Source: | Automatika: Journal for Control, Measurement, Electronics, Computing & Communications. Dec2025, Vol. 66 Issue 4, p22-31. 10p. |
| Subjects: | Multiplication, Algorithms, Matrix decomposition, Binary operations, Time complexity, Very large scale circuit integration, Embedded computer systems, Computer performance |
| Abstract: | Binary multiplication is a key operation in digital systems, often limited by the complexity of generating and summing numerous partial products. Traditional methods, like Booth's algorithm, produce a summand matrix proportional to the operand bit-length, increasing computational load, hardware usage and latency. To address these issues, we propose a novel binary multiplication algorithm that minimizes the number of required summands. By selectively using the smaller operand and employing targeted shift operations, our method avoids recursive bit-level multiplications and reduces summands to as few as 1–5 for odd and 1–4 for even operands. This approach achieves a lower time complexity of O(log2n), offering significant speed improvements over existing algorithms. Moreover, it leads to a reduction in hardware components by approximately 40–75%, contributing to notable power savings. The algorithm is fully compatible with existing parallel adder circuits, ensuring ease of integration. Its simplicity and efficiency make it ideal for low-power arithmetic units, embedded systems and DSP applications. Future work will focus on supporting signed multiplications and integrating the algorithm into VLSI designs for real-world applications, enhancing its appeal in resource-constrained computing environments. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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| Abstract: | Binary multiplication is a key operation in digital systems, often limited by the complexity of generating and summing numerous partial products. Traditional methods, like Booth's algorithm, produce a summand matrix proportional to the operand bit-length, increasing computational load, hardware usage and latency. To address these issues, we propose a novel binary multiplication algorithm that minimizes the number of required summands. By selectively using the smaller operand and employing targeted shift operations, our method avoids recursive bit-level multiplications and reduces summands to as few as 1–5 for odd and 1–4 for even operands. This approach achieves a lower time complexity of O(log2n), offering significant speed improvements over existing algorithms. Moreover, it leads to a reduction in hardware components by approximately 40–75%, contributing to notable power savings. The algorithm is fully compatible with existing parallel adder circuits, ensuring ease of integration. Its simplicity and efficiency make it ideal for low-power arithmetic units, embedded systems and DSP applications. Future work will focus on supporting signed multiplications and integrating the algorithm into VLSI designs for real-world applications, enhancing its appeal in resource-constrained computing environments. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 00051144 |
| DOI: | 10.1080/00051144.2025.2526261 |
