View in EDS HTML Full Text PDF Full Text

An efficient algorithmic framework to minimize the summand matrix in binary multiplication.

Saved in:
Bibliographic Details
Title: An efficient algorithmic framework to minimize the summand matrix in binary multiplication.
Authors: Verma, Amit1 (AUTHOR), Prateek, Manish2 (AUTHOR), Shivhare, Shiv Naresh3 (AUTHOR), Singh, Thipendra P.3 (AUTHOR), Kumar, Anuj4 (AUTHOR), Ranjan, Rakesh1 (AUTHOR), Priyadarshi, Rahul5 (AUTHOR) rahul.glorious91@gmail.com
Source: Automatika: Journal for Control, Measurement, Electronics, Computing & Communications. Dec2025, Vol. 66 Issue 4, p22-31. 10p.
Subjects: Multiplication, Algorithms, Matrix decomposition, Binary operations, Time complexity, Very large scale circuit integration, Embedded computer systems, Computer performance
Abstract: Binary multiplication is a key operation in digital systems, often limited by the complexity of generating and summing numerous partial products. Traditional methods, like Booth's algorithm, produce a summand matrix proportional to the operand bit-length, increasing computational load, hardware usage and latency. To address these issues, we propose a novel binary multiplication algorithm that minimizes the number of required summands. By selectively using the smaller operand and employing targeted shift operations, our method avoids recursive bit-level multiplications and reduces summands to as few as 1–5 for odd and 1–4 for even operands. This approach achieves a lower time complexity of O(log2n), offering significant speed improvements over existing algorithms. Moreover, it leads to a reduction in hardware components by approximately 40–75%, contributing to notable power savings. The algorithm is fully compatible with existing parallel adder circuits, ensuring ease of integration. Its simplicity and efficiency make it ideal for low-power arithmetic units, embedded systems and DSP applications. Future work will focus on supporting signed multiplications and integrating the algorithm into VLSI designs for real-world applications, enhancing its appeal in resource-constrained computing environments. [ABSTRACT FROM AUTHOR]
Copyright of Automatika: Journal for Control, Measurement, Electronics, Computing & Communications is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
Full text is not displayed to guests.
FullText Links:
  – Type: pdflink
Text:
  Availability: 1
Header DbId: egs
DbLabel: Engineering Source
An: 189685956
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: An efficient algorithmic framework to minimize the summand matrix in binary multiplication.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Verma%2C+Amit%22">Verma, Amit</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Prateek%2C+Manish%22">Prateek, Manish</searchLink><relatesTo>2</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Shivhare%2C+Shiv+Naresh%22">Shivhare, Shiv Naresh</searchLink><relatesTo>3</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Singh%2C+Thipendra+P%2E%22">Singh, Thipendra P.</searchLink><relatesTo>3</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Kumar%2C+Anuj%22">Kumar, Anuj</searchLink><relatesTo>4</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Ranjan%2C+Rakesh%22">Ranjan, Rakesh</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Priyadarshi%2C+Rahul%22">Priyadarshi, Rahul</searchLink><relatesTo>5</relatesTo> (AUTHOR)<i> rahul.glorious91@gmail.com</i>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Automatika%3A+Journal+for+Control%2C+Measurement%2C+Electronics%2C+Computing+%26+Communications%22">Automatika: Journal for Control, Measurement, Electronics, Computing & Communications</searchLink>. Dec2025, Vol. 66 Issue 4, p22-31. 10p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Multiplication%22">Multiplication</searchLink><br /><searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Matrix+decomposition%22">Matrix decomposition</searchLink><br /><searchLink fieldCode="DE" term="%22Binary+operations%22">Binary operations</searchLink><br /><searchLink fieldCode="DE" term="%22Time+complexity%22">Time complexity</searchLink><br /><searchLink fieldCode="DE" term="%22Very+large+scale+circuit+integration%22">Very large scale circuit integration</searchLink><br /><searchLink fieldCode="DE" term="%22Embedded+computer+systems%22">Embedded computer systems</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+performance%22">Computer performance</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: Binary multiplication is a key operation in digital systems, often limited by the complexity of generating and summing numerous partial products. Traditional methods, like Booth's algorithm, produce a summand matrix proportional to the operand bit-length, increasing computational load, hardware usage and latency. To address these issues, we propose a novel binary multiplication algorithm that minimizes the number of required summands. By selectively using the smaller operand and employing targeted shift operations, our method avoids recursive bit-level multiplications and reduces summands to as few as 1–5 for odd and 1–4 for even operands. This approach achieves a lower time complexity of O(log2n), offering significant speed improvements over existing algorithms. Moreover, it leads to a reduction in hardware components by approximately 40–75%, contributing to notable power savings. The algorithm is fully compatible with existing parallel adder circuits, ensuring ease of integration. Its simplicity and efficiency make it ideal for low-power arithmetic units, embedded systems and DSP applications. Future work will focus on supporting signed multiplications and integrating the algorithm into VLSI designs for real-world applications, enhancing its appeal in resource-constrained computing environments. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Automatika: Journal for Control, Measurement, Electronics, Computing & Communications is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=189685956
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1080/00051144.2025.2526261
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 10
        StartPage: 22
    Subjects:
      – SubjectFull: Multiplication
        Type: general
      – SubjectFull: Algorithms
        Type: general
      – SubjectFull: Matrix decomposition
        Type: general
      – SubjectFull: Binary operations
        Type: general
      – SubjectFull: Time complexity
        Type: general
      – SubjectFull: Very large scale circuit integration
        Type: general
      – SubjectFull: Embedded computer systems
        Type: general
      – SubjectFull: Computer performance
        Type: general
    Titles:
      – TitleFull: An efficient algorithmic framework to minimize the summand matrix in binary multiplication.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Verma, Amit
      – PersonEntity:
          Name:
            NameFull: Prateek, Manish
      – PersonEntity:
          Name:
            NameFull: Shivhare, Shiv Naresh
      – PersonEntity:
          Name:
            NameFull: Singh, Thipendra P.
      – PersonEntity:
          Name:
            NameFull: Kumar, Anuj
      – PersonEntity:
          Name:
            NameFull: Ranjan, Rakesh
      – PersonEntity:
          Name:
            NameFull: Priyadarshi, Rahul
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 12
              Text: Dec2025
              Type: published
              Y: 2025
          Identifiers:
            – Type: issn-print
              Value: 00051144
          Numbering:
            – Type: volume
              Value: 66
            – Type: issue
              Value: 4
          Titles:
            – TitleFull: Automatika: Journal for Control, Measurement, Electronics, Computing & Communications
              Type: main
ResultId 1