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Does the ISA really matter? --A survey of simulations based on Gem5.

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Title: Does the ISA really matter? --A survey of simulations based on Gem5.
Authors: LI, Hua1,2, WANG, Yongwen1,2 yongwen@nudt.edu.cn
Source: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Nov2025, Vol. 47 Issue 11, p1945-1952. 8p.
Subjects: Instruction set architecture, Electric power consumption, Simulation methods & models, Benchmark problems (Computer science), Instruction set processors, Emulation software, Reduced instruction set computers
Abstract: The instruction set architecture (ISA) serves as the foundational framework of a chip, yet existing research on its performance impact often relies on real hardware implementations. However, varying hardware setups pose challenges for direct comparison and analysis of ISAs. To address this issue, simulations of ARM, RISC-V, and x86 ISAs were conducted using the Gem5 simulator, using identical hardware configurations and the same compiler version, thereby enabling a controlled comparative analysis. CoreMark, Dhrystone, and Whetstone are adopted as benchmark programs, while McPAT assesses power consumption. Results from the simulations reveal that the ARM ISA exhibits superior performance and lower power consumption compared to RISC-V and x86 ISAs. Although differences between ARM and RISC-V are marginal, the performance gap between ARM and x86 may stem from the relatively modest hardware configuration utilized, which could be mitigated or reversed through the adoption of more aggressive hardware techniques. This research underscores that while an ISA plays a pivotal role, solely relying on it cannot fundamentally enhance efficiency. [ABSTRACT FROM AUTHOR]
Copyright of Computer Engineering & Science / Jisuanji Gongcheng yu Kexue is the property of Computer Engineering & Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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  Data: Does the ISA really matter? --A survey of simulations based on Gem5.
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  Data: <searchLink fieldCode="DE" term="%22Instruction+set+architecture%22">Instruction set architecture</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+power+consumption%22">Electric power consumption</searchLink><br /><searchLink fieldCode="DE" term="%22Simulation+methods+%26+models%22">Simulation methods & models</searchLink><br /><searchLink fieldCode="DE" term="%22Benchmark+problems+%28Computer+science%29%22">Benchmark problems (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22Instruction+set+processors%22">Instruction set processors</searchLink><br /><searchLink fieldCode="DE" term="%22Emulation+software%22">Emulation software</searchLink><br /><searchLink fieldCode="DE" term="%22Reduced+instruction+set+computers%22">Reduced instruction set computers</searchLink>
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  Data: The instruction set architecture (ISA) serves as the foundational framework of a chip, yet existing research on its performance impact often relies on real hardware implementations. However, varying hardware setups pose challenges for direct comparison and analysis of ISAs. To address this issue, simulations of ARM, RISC-V, and x86 ISAs were conducted using the Gem5 simulator, using identical hardware configurations and the same compiler version, thereby enabling a controlled comparative analysis. CoreMark, Dhrystone, and Whetstone are adopted as benchmark programs, while McPAT assesses power consumption. Results from the simulations reveal that the ARM ISA exhibits superior performance and lower power consumption compared to RISC-V and x86 ISAs. Although differences between ARM and RISC-V are marginal, the performance gap between ARM and x86 may stem from the relatively modest hardware configuration utilized, which could be mitigated or reversed through the adoption of more aggressive hardware techniques. This research underscores that while an ISA plays a pivotal role, solely relying on it cannot fundamentally enhance efficiency. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Computer Engineering & Science / Jisuanji Gongcheng yu Kexue is the property of Computer Engineering & Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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      – Type: doi
        Value: 10.3969/j.issn.1007-130X.2025.11.005
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      – Code: chi
        Text: Chinese
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        PageCount: 8
        StartPage: 1945
    Subjects:
      – SubjectFull: Instruction set architecture
        Type: general
      – SubjectFull: Electric power consumption
        Type: general
      – SubjectFull: Simulation methods & models
        Type: general
      – SubjectFull: Benchmark problems (Computer science)
        Type: general
      – SubjectFull: Instruction set processors
        Type: general
      – SubjectFull: Emulation software
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      – SubjectFull: Reduced instruction set computers
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            – D: 01
              M: 11
              Text: Nov2025
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              Y: 2025
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