A hybrid matrix-vector processor with dynamically reconfigurable dataflow.
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| Title: | A hybrid matrix-vector processor with dynamically reconfigurable dataflow. |
|---|---|
| Authors: | AI, Chenyang1, ZHAO, Lechuan1, HUA, Tao1, WANG, Xin'an1 anxinwang@pku.edu.cn, WANG, Ying2 |
| Source: | Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Nov2025, Vol. 47 Issue 11, p1912-1921. 10p. |
| Subjects: | Matrix multiplications, Array processors, High performance processors, Coprocessors, Adaptive computing systems |
| Abstract: | Systolic arrays, as energy-efficient accelerators for general matrix multiplication (GEMM) operators, have garnered widespread attention from both academia and industry. However, they often occupy a substantial amount of area and typically require collaboration with VPU (vector processing unit) components, a combination frequently seen in neural network accelerators. Additionally, they suffer from issues such as low temporal and spatial utilization rates and limited performance in end-to-end scenarios. To address these challenges, a hybrid vector systolic array (HVSA) is proposed by integrating systolic arrays with vector processors. By reusing the storage, broadcasting, and inter-channel communication units within the VPU, this architecture enables reconfigurable capabilities in terms of array shape and data flow, allowing for more efficient support of GEMM and vector operations within an acceptable hardware area overhead. Furthermore, an end-to-end compilation framework tailored for HVSA is introduced, encompassing an MLIR-based compilation front end, data flow scheduling, and a programming model compatible with the RISC-V vector extension. Experimental data demonstrates that HVSA achieves a 30.30-fold increase in computational speed compared to a systolic array of equivalent area. In end-to-end applications, the average operating time of HVSA is reduced to around 4.7% of the original compared to the "VPU+SA" of the same area, and energy consumption is reduced by approximately 58.7%. [ABSTRACT FROM AUTHOR] |
| Copyright of Computer Engineering & Science / Jisuanji Gongcheng yu Kexue is the property of Computer Engineering & Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 190505674 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: A hybrid matrix-vector processor with dynamically reconfigurable dataflow. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22AI%2C+Chenyang%22">AI, Chenyang</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22ZHAO%2C+Lechuan%22">ZHAO, Lechuan</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22HUA%2C+Tao%22">HUA, Tao</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22WANG%2C+Xin'an%22">WANG, Xin'an</searchLink><relatesTo>1</relatesTo><i> anxinwang@pku.edu.cn</i><br /><searchLink fieldCode="AR" term="%22WANG%2C+Ying%22">WANG, Ying</searchLink><relatesTo>2</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Computer+Engineering+%26+Science+%2F+Jisuanji+Gongcheng+yu+Kexue%22">Computer Engineering & Science / Jisuanji Gongcheng yu Kexue</searchLink>. Nov2025, Vol. 47 Issue 11, p1912-1921. 10p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Matrix+multiplications%22">Matrix multiplications</searchLink><br /><searchLink fieldCode="DE" term="%22Array+processors%22">Array processors</searchLink><br /><searchLink fieldCode="DE" term="%22High+performance+processors%22">High performance processors</searchLink><br /><searchLink fieldCode="DE" term="%22Coprocessors%22">Coprocessors</searchLink><br /><searchLink fieldCode="DE" term="%22Adaptive+computing+systems%22">Adaptive computing systems</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Systolic arrays, as energy-efficient accelerators for general matrix multiplication (GEMM) operators, have garnered widespread attention from both academia and industry. However, they often occupy a substantial amount of area and typically require collaboration with VPU (vector processing unit) components, a combination frequently seen in neural network accelerators. Additionally, they suffer from issues such as low temporal and spatial utilization rates and limited performance in end-to-end scenarios. To address these challenges, a hybrid vector systolic array (HVSA) is proposed by integrating systolic arrays with vector processors. By reusing the storage, broadcasting, and inter-channel communication units within the VPU, this architecture enables reconfigurable capabilities in terms of array shape and data flow, allowing for more efficient support of GEMM and vector operations within an acceptable hardware area overhead. Furthermore, an end-to-end compilation framework tailored for HVSA is introduced, encompassing an MLIR-based compilation front end, data flow scheduling, and a programming model compatible with the RISC-V vector extension. Experimental data demonstrates that HVSA achieves a 30.30-fold increase in computational speed compared to a systolic array of equivalent area. In end-to-end applications, the average operating time of HVSA is reduced to around 4.7% of the original compared to the "VPU+SA" of the same area, and energy consumption is reduced by approximately 58.7%. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Computer Engineering & Science / Jisuanji Gongcheng yu Kexue is the property of Computer Engineering & Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.3969/j.issn.1007-130X.2025.11.002 Languages: – Code: chi Text: Chinese PhysicalDescription: Pagination: PageCount: 10 StartPage: 1912 Subjects: – SubjectFull: Matrix multiplications Type: general – SubjectFull: Array processors Type: general – SubjectFull: High performance processors Type: general – SubjectFull: Coprocessors Type: general – SubjectFull: Adaptive computing systems Type: general Titles: – TitleFull: A hybrid matrix-vector processor with dynamically reconfigurable dataflow. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: AI, Chenyang – PersonEntity: Name: NameFull: ZHAO, Lechuan – PersonEntity: Name: NameFull: HUA, Tao – PersonEntity: Name: NameFull: WANG, Xin'an – PersonEntity: Name: NameFull: WANG, Ying IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 11 Text: Nov2025 Type: published Y: 2025 Identifiers: – Type: issn-print Value: 1007130X Numbering: – Type: volume Value: 47 – Type: issue Value: 11 Titles: – TitleFull: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue Type: main |
| ResultId | 1 |
