Configurable CPU performance analysis method for specific applications.
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| Title: | Configurable CPU performance analysis method for specific applications. |
|---|---|
| Authors: | DENG, Quan1,2, LIN, Rongzhen1,2, LUO, Li1,2, LU, Jianzhuang1,2, WANG, Yongwen1,2 yongwen@nudt.edu.cn |
| Source: | Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Nov2025, Vol. 47 Issue 11, p1901-1911. 11p. |
| Subjects: | Computer performance, Reduced instruction set computers, Hardware, Benchmark problems (Computer science), Hypothesis, Modular design |
| Abstract: | With the development of integrated circuits and the continuous expansion of chip applications, configurable CPU facilitates the exploration of the chip design space. Configurable CPU can not only meet the demands of agile design but also cater to users' needs for tuning based on target applications. However, at present, the performance tuning of application-specific configurable CPU still primarily relies on experienced architecture engineers, lacking a set of scientific methodologies for guidance. Therefore, this paper proposes a configurable CPU performance analysis method for specific applications. At the software level, the Perf tool is utilized to quickly identify hot code blocks in applications during hardware execution. At the hardware level, by analyzing two counting modes (counting of cycles and counting of slots) within the analysis framework, the hot execution conditions of each execution unit are pinpointed, enabling designers to swiftly locate hot behaviors in hardware execution. This paper conducts agile design for a configurable DMR (dual-module redundancy) architecture supporting the RISC-V instruction set using the typical fluid dynamics program NPB (NAS parallel benchmark). The experimental results indicate a 13.2% improvement in single-core performance of the configurable CPU, with a 12.2% increase in area overhead. [ABSTRACT FROM AUTHOR] |
| Copyright of Computer Engineering & Science / Jisuanji Gongcheng yu Kexue is the property of Computer Engineering & Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 190505688 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Configurable CPU performance analysis method for specific applications. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22DENG%2C+Quan%22">DENG, Quan</searchLink><relatesTo>1,2</relatesTo><br /><searchLink fieldCode="AR" term="%22LIN%2C+Rongzhen%22">LIN, Rongzhen</searchLink><relatesTo>1,2</relatesTo><br /><searchLink fieldCode="AR" term="%22LUO%2C+Li%22">LUO, Li</searchLink><relatesTo>1,2</relatesTo><br /><searchLink fieldCode="AR" term="%22LU%2C+Jianzhuang%22">LU, Jianzhuang</searchLink><relatesTo>1,2</relatesTo><br /><searchLink fieldCode="AR" term="%22WANG%2C+Yongwen%22">WANG, Yongwen</searchLink><relatesTo>1,2</relatesTo><i> yongwen@nudt.edu.cn</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Computer+Engineering+%26+Science+%2F+Jisuanji+Gongcheng+yu+Kexue%22">Computer Engineering & Science / Jisuanji Gongcheng yu Kexue</searchLink>. Nov2025, Vol. 47 Issue 11, p1901-1911. 11p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Computer+performance%22">Computer performance</searchLink><br /><searchLink fieldCode="DE" term="%22Reduced+instruction+set+computers%22">Reduced instruction set computers</searchLink><br /><searchLink fieldCode="DE" term="%22Hardware%22">Hardware</searchLink><br /><searchLink fieldCode="DE" term="%22Benchmark+problems+%28Computer+science%29%22">Benchmark problems (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22Hypothesis%22">Hypothesis</searchLink><br /><searchLink fieldCode="DE" term="%22Modular+design%22">Modular design</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: With the development of integrated circuits and the continuous expansion of chip applications, configurable CPU facilitates the exploration of the chip design space. Configurable CPU can not only meet the demands of agile design but also cater to users' needs for tuning based on target applications. However, at present, the performance tuning of application-specific configurable CPU still primarily relies on experienced architecture engineers, lacking a set of scientific methodologies for guidance. Therefore, this paper proposes a configurable CPU performance analysis method for specific applications. At the software level, the Perf tool is utilized to quickly identify hot code blocks in applications during hardware execution. At the hardware level, by analyzing two counting modes (counting of cycles and counting of slots) within the analysis framework, the hot execution conditions of each execution unit are pinpointed, enabling designers to swiftly locate hot behaviors in hardware execution. This paper conducts agile design for a configurable DMR (dual-module redundancy) architecture supporting the RISC-V instruction set using the typical fluid dynamics program NPB (NAS parallel benchmark). The experimental results indicate a 13.2% improvement in single-core performance of the configurable CPU, with a 12.2% increase in area overhead. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Computer Engineering & Science / Jisuanji Gongcheng yu Kexue is the property of Computer Engineering & Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.3969/j.issn.1007-130X.2025.11.001 Languages: – Code: chi Text: Chinese PhysicalDescription: Pagination: PageCount: 11 StartPage: 1901 Subjects: – SubjectFull: Computer performance Type: general – SubjectFull: Reduced instruction set computers Type: general – SubjectFull: Hardware Type: general – SubjectFull: Benchmark problems (Computer science) Type: general – SubjectFull: Hypothesis Type: general – SubjectFull: Modular design Type: general Titles: – TitleFull: Configurable CPU performance analysis method for specific applications. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: DENG, Quan – PersonEntity: Name: NameFull: LIN, Rongzhen – PersonEntity: Name: NameFull: LUO, Li – PersonEntity: Name: NameFull: LU, Jianzhuang – PersonEntity: Name: NameFull: WANG, Yongwen IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 11 Text: Nov2025 Type: published Y: 2025 Identifiers: – Type: issn-print Value: 1007130X Numbering: – Type: volume Value: 47 – Type: issue Value: 11 Titles: – TitleFull: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue Type: main |
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