Improving the Performance of Turbo Codes With a Simple Protection Scheme for Error-Prone Bit Positions.
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| Title: | Improving the Performance of Turbo Codes With a Simple Protection Scheme for Error-Prone Bit Positions. |
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| Authors: | Wangrok Oh1 kingrock@postech.ac.kr, Youhan Kim1, Kyungwhoon Cheun1 cheun@postech.ac.kr |
| Source: | IEEE Transactions on Communications. Nov2005, Vol. 53 Issue 11, p1777-1781. 5p. |
| Subjects: | Turbo languages (Computer program language), Programming languages, Microprocessors, Error functions, Definite integrals, Probability theory |
| Abstract: | It is well known that turbo codes provide highly unequal error protection within a transmitted frame. Previous attempts to exploit this fact focused mainly on adding additional redundancy to provide extra protection for the error-prone bit positions. Here, instead, we use the error-detection capability of the cyclic redundancy check (CRC), which is almost always employed in practical systems. Once a frame is declared uncorrectable by the CRC, a process termed the error-prone bit processing procedure is activated in an attempt to correct the probable error patterns which are a priori identified as being error-prone. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Transactions on Communications is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 19123964 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Improving the Performance of Turbo Codes With a Simple Protection Scheme for Error-Prone Bit Positions. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Wangrok+Oh%22">Wangrok Oh</searchLink><relatesTo>1</relatesTo><i> kingrock@postech.ac.kr</i><br /><searchLink fieldCode="AR" term="%22Youhan+Kim%22">Youhan Kim</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Kyungwhoon+Cheun%22">Kyungwhoon Cheun</searchLink><relatesTo>1</relatesTo><i> cheun@postech.ac.kr</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Communications%22">IEEE Transactions on Communications</searchLink>. Nov2005, Vol. 53 Issue 11, p1777-1781. 5p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Turbo+languages+%28Computer+program+language%29%22">Turbo languages (Computer program language)</searchLink><br /><searchLink fieldCode="DE" term="%22Programming+languages%22">Programming languages</searchLink><br /><searchLink fieldCode="DE" term="%22Microprocessors%22">Microprocessors</searchLink><br /><searchLink fieldCode="DE" term="%22Error+functions%22">Error functions</searchLink><br /><searchLink fieldCode="DE" term="%22Definite+integrals%22">Definite integrals</searchLink><br /><searchLink fieldCode="DE" term="%22Probability+theory%22">Probability theory</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: It is well known that turbo codes provide highly unequal error protection within a transmitted frame. Previous attempts to exploit this fact focused mainly on adding additional redundancy to provide extra protection for the error-prone bit positions. Here, instead, we use the error-detection capability of the cyclic redundancy check (CRC), which is almost always employed in practical systems. Once a frame is declared uncorrectable by the CRC, a process termed the error-prone bit processing procedure is activated in an attempt to correct the probable error patterns which are a priori identified as being error-prone. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Communications is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TCOMM.2005.858653 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 5 StartPage: 1777 Subjects: – SubjectFull: Turbo languages (Computer program language) Type: general – SubjectFull: Programming languages Type: general – SubjectFull: Microprocessors Type: general – SubjectFull: Error functions Type: general – SubjectFull: Definite integrals Type: general – SubjectFull: Probability theory Type: general Titles: – TitleFull: Improving the Performance of Turbo Codes With a Simple Protection Scheme for Error-Prone Bit Positions. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Wangrok Oh – PersonEntity: Name: NameFull: Youhan Kim – PersonEntity: Name: NameFull: Kyungwhoon Cheun IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 11 Text: Nov2005 Type: published Y: 2005 Identifiers: – Type: issn-print Value: 00906778 Numbering: – Type: volume Value: 53 – Type: issue Value: 11 Titles: – TitleFull: IEEE Transactions on Communications Type: main |
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