Variable-Size Interleaver Design for Parallel Turbo Decoder Architectures.

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Title: Variable-Size Interleaver Design for Parallel Turbo Decoder Architectures.
Authors: Dinoi, Libero1 dinoi@ismb.it, Benedetto, Sergio2 benedetto@polito.it
Source: IEEE Transactions on Communications. Nov2005, Vol. 53 Issue 11, p1833-1840. 8p.
Subjects: Turbo languages (Computer program language), Decoders (Electronics), Coding theory, Probability theory, Estimation theory, Mathematical combinations
Abstract: In this paper, we propose two techniques to design good S-random interleavers, to be used in parallel and serially concatenated codes with interleavers. The interleavers designed according to these algorithms can be shortened, in order to support different block lengths in such a way that all the permutations obtained by pruning, when employed in a parallel turbo decoder, are collision-free. The first technique, suitable for short and medium interleavers, guarantees the same performance of non- parallel interleavers in terms of spreading properties, simulated frame-error probabilities, and obtainable minimum distance of the actual codes. The second algorithm, to be used for large block lengths, permits achieving high degrees of parallelism at the price of a slight degradation of the spread properties, and also to change the degree of parallelism on-the-fly. The operations of a parallel turbo decoder employing these interleavers are described, and an example of the advantages of the proposed techniques is provided in a realistic system framework. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Transactions on Communications is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: Variable-Size Interleaver Design for Parallel Turbo Decoder Architectures.
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  Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Communications%22">IEEE Transactions on Communications</searchLink>. Nov2005, Vol. 53 Issue 11, p1833-1840. 8p.
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  Data: <searchLink fieldCode="DE" term="%22Turbo+languages+%28Computer+program+language%29%22">Turbo languages (Computer program language)</searchLink><br /><searchLink fieldCode="DE" term="%22Decoders+%28Electronics%29%22">Decoders (Electronics)</searchLink><br /><searchLink fieldCode="DE" term="%22Coding+theory%22">Coding theory</searchLink><br /><searchLink fieldCode="DE" term="%22Probability+theory%22">Probability theory</searchLink><br /><searchLink fieldCode="DE" term="%22Estimation+theory%22">Estimation theory</searchLink><br /><searchLink fieldCode="DE" term="%22Mathematical+combinations%22">Mathematical combinations</searchLink>
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  Data: In this paper, we propose two techniques to design good S-random interleavers, to be used in parallel and serially concatenated codes with interleavers. The interleavers designed according to these algorithms can be shortened, in order to support different block lengths in such a way that all the permutations obtained by pruning, when employed in a parallel turbo decoder, are collision-free. The first technique, suitable for short and medium interleavers, guarantees the same performance of non- parallel interleavers in terms of spreading properties, simulated frame-error probabilities, and obtainable minimum distance of the actual codes. The second algorithm, to be used for large block lengths, permits achieving high degrees of parallelism at the price of a slight degradation of the spread properties, and also to change the degree of parallelism on-the-fly. The operations of a parallel turbo decoder employing these interleavers are described, and an example of the advantages of the proposed techniques is provided in a realistic system framework. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of IEEE Transactions on Communications is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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      – Type: doi
        Value: 10.1109/TCOMM.2005.858685
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      – Code: eng
        Text: English
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      Pagination:
        PageCount: 8
        StartPage: 1833
    Subjects:
      – SubjectFull: Turbo languages (Computer program language)
        Type: general
      – SubjectFull: Decoders (Electronics)
        Type: general
      – SubjectFull: Coding theory
        Type: general
      – SubjectFull: Probability theory
        Type: general
      – SubjectFull: Estimation theory
        Type: general
      – SubjectFull: Mathematical combinations
        Type: general
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      – TitleFull: Variable-Size Interleaver Design for Parallel Turbo Decoder Architectures.
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              M: 11
              Text: Nov2005
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              Y: 2005
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