Exploring Efficient FPGA Acceleration of High-Order 3D Iterative Stencil Loops on Large Data Grids.
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| Title: | Exploring Efficient FPGA Acceleration of High-Order 3D Iterative Stencil Loops on Large Data Grids. |
|---|---|
| Authors: | Ibrahim, Alhussain1 (AUTHOR) aibrahim@palmlab.com, Elrabaa, Muhammad E. S.2 (AUTHOR) elrabaa@kfupm.edu.sa, Alsaleh, Saleh2 (AUTHOR) salehs@kfupm.edu.sa, El-Maleh, Aiman H.2 (AUTHOR) aimane@kfupm.edu.sa, Tonellot, Thierry3 (AUTHOR) thierrylaurent.tonellot@aramco.com |
| Source: | Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ). Jan2026, Vol. 51 Issue 1, p205-222. 18p. |
| Subjects: | Field programmable gate arrays, Iterative methods (Mathematics), Resource allocation, Tiling (Mathematics), Time |
| Abstract: | An efficient methodology for FPGA acceleration of high-order 3D iterative stencil loops over large 3D-grids was developed. Spatial (tiling) and temporal (combined iterations) blocking are used to circumvent the FPGAs' limitations and maximize throughput. Implemented as a fully asynchronous SW-HW pipeline, it can compute high-order stencils on 3D grid without any limitations on the grid size or the number of iterations. An 8th-order, 25-point 3D stencil was used to demonstrate the methodology and possible optimizations of performance, resource utilization, and power efficiency. Results show that throughput is only limited by the FPGA off-chip memory bandwidth. Comparisons with published results for the same stencil showed that the developed methodology can achieve a throughput equivalent to ~ 43-Haswell cores (22 nm technology) or ~ 13 Milan-x cores (7 nm technology) running at 2.3 and 2.45 GHz, respectively. Compared to an A100 NVIDIA GPU implementation of the same stencil, it achieved ~ 41% better power efficiency (Watts per GB/s). The methodology was extended to support multiple FPGAs. With two FPGA boards, the total latency was reduced by ~ 27%. [ABSTRACT FROM AUTHOR] |
| Copyright of Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ) is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 191806086 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Exploring Efficient FPGA Acceleration of High-Order 3D Iterative Stencil Loops on Large Data Grids. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Ibrahim%2C+Alhussain%22">Ibrahim, Alhussain</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> aibrahim@palmlab.com</i><br /><searchLink fieldCode="AR" term="%22Elrabaa%2C+Muhammad+E%2E+S%2E%22">Elrabaa, Muhammad E. S.</searchLink><relatesTo>2</relatesTo> (AUTHOR)<i> elrabaa@kfupm.edu.sa</i><br /><searchLink fieldCode="AR" term="%22Alsaleh%2C+Saleh%22">Alsaleh, Saleh</searchLink><relatesTo>2</relatesTo> (AUTHOR)<i> salehs@kfupm.edu.sa</i><br /><searchLink fieldCode="AR" term="%22El-Maleh%2C+Aiman+H%2E%22">El-Maleh, Aiman H.</searchLink><relatesTo>2</relatesTo> (AUTHOR)<i> aimane@kfupm.edu.sa</i><br /><searchLink fieldCode="AR" term="%22Tonellot%2C+Thierry%22">Tonellot, Thierry</searchLink><relatesTo>3</relatesTo> (AUTHOR)<i> thierrylaurent.tonellot@aramco.com</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Arabian+Journal+for+Science+%26+Engineering+%28Springer+Science+%26+Business+Media+B%2EV%2E+%29%22">Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. )</searchLink>. Jan2026, Vol. 51 Issue 1, p205-222. 18p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Iterative+methods+%28Mathematics%29%22">Iterative methods (Mathematics)</searchLink><br /><searchLink fieldCode="DE" term="%22Resource+allocation%22">Resource allocation</searchLink><br /><searchLink fieldCode="DE" term="%22Tiling+%28Mathematics%29%22">Tiling (Mathematics)</searchLink><br /><searchLink fieldCode="DE" term="%22Time%22">Time</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: An efficient methodology for FPGA acceleration of high-order 3D iterative stencil loops over large 3D-grids was developed. Spatial (tiling) and temporal (combined iterations) blocking are used to circumvent the FPGAs' limitations and maximize throughput. Implemented as a fully asynchronous SW-HW pipeline, it can compute high-order stencils on 3D grid without any limitations on the grid size or the number of iterations. An 8th-order, 25-point 3D stencil was used to demonstrate the methodology and possible optimizations of performance, resource utilization, and power efficiency. Results show that throughput is only limited by the FPGA off-chip memory bandwidth. Comparisons with published results for the same stencil showed that the developed methodology can achieve a throughput equivalent to ~ 43-Haswell cores (22 nm technology) or ~ 13 Milan-x cores (7 nm technology) running at 2.3 and 2.45 GHz, respectively. Compared to an A100 NVIDIA GPU implementation of the same stencil, it achieved ~ 41% better power efficiency (Watts per GB/s). The methodology was extended to support multiple FPGAs. With two FPGA boards, the total latency was reduced by ~ 27%. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ) is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s13369-025-10919-y Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 18 StartPage: 205 Subjects: – SubjectFull: Field programmable gate arrays Type: general – SubjectFull: Iterative methods (Mathematics) Type: general – SubjectFull: Resource allocation Type: general – SubjectFull: Tiling (Mathematics) Type: general – SubjectFull: Time Type: general Titles: – TitleFull: Exploring Efficient FPGA Acceleration of High-Order 3D Iterative Stencil Loops on Large Data Grids. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Ibrahim, Alhussain – PersonEntity: Name: NameFull: Elrabaa, Muhammad E. S. – PersonEntity: Name: NameFull: Alsaleh, Saleh – PersonEntity: Name: NameFull: El-Maleh, Aiman H. – PersonEntity: Name: NameFull: Tonellot, Thierry IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Text: Jan2026 Type: published Y: 2026 Identifiers: – Type: issn-print Value: 2193567X Numbering: – Type: volume Value: 51 – Type: issue Value: 1 Titles: – TitleFull: Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ) Type: main |
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