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Efficient Implementation of Fixed-Point MAC and Multimode MAC Blocks Based on Vedic Mathematic.

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Title: Efficient Implementation of Fixed-Point MAC and Multimode MAC Blocks Based on Vedic Mathematic.
Authors: Hussein, Fatima Tariq1 pgs.fatima.tariq@uobasrah.edu.iq, AL-Assfor, Fatemah K.1
Source: Iraqi Journal for Electrical & Electronic Engineering. Dec2025, Vol. 21 Issue 2, p88-98. 11p.
Subjects: Field programmable gate arrays, Digital signal processing, Mathematics, Addition (Mathematics), Engineering design
Abstract (English): Recently, the need for high speed multiply-accumulate (MAC) operations is crucial in numerous systems like 5G, deep learning, in addition to many digital signal processing (DSP) applications. This work offers an improved MAC (I-MAC) block of different bit-size based on Vedic Mathematic and employing a hybrid adder consists of an enhanced Brent-Kung with a carry-select adder (HBK-CSLA) to achieve the sum of products for the MAC. The work is then, developed to design a new multimode fixed-point (FX-Pt) MAC block by exploiting the proposed design of the I-MAC architecture. The proposed multimode MAC block supports three modes of operation; single 64-bit MAC operation, dual 32-bit multiplication with 32-bit single addition, and single 32-bit MAC operation. The design has utilized an adjusted architecture for the Vedic-multiplier (Adjusted-VM), a 64-bit HBK-CSLA, and a control circuit to select the desired mode of operation. The performance of the multi-mode MAC is then optimized by exploiting pipelining concept. The proposed architectures are synthesized in various FPGA families utilizing VHDL language in Xilinx ISE14.7 tool. The performance results have exposed that the proposed 64-bit I-MAC block have attained observable lessen 9.767% in delay and area usage of 47.49% compared with the most existing MAC block designs. [ABSTRACT FROM AUTHOR]
Abstract (Arabic): يركز المقال على تصميم وتنفيذ وحدات الضرب-التراكم (MAC) ذات النقطة الثابتة الفعالة وكتل MAC متعددة الأنماط المستندة إلى الرياضيات الفيدية (الرياضيات الفيدية) لتطبيقات معالجة الإشارات الرقمية (DSP) والتعلم العميق. يقدم المقال بنية محسنة لوحدة MAC (I-MAC) تستخدم مضاعف فيدي معدل (المضاعف الفيدي المعدل) مدمجًا مع جامع هجيني—وهو جامع برنت-كونغ المحسن وجامع اختيار الحمل (HBK-CSLA)—لتحسين السرعة واستخدام المساحة عبر عرضات بت مختلفة (8، 16، 32، و64 بت). بالإضافة إلى ذلك، تم تطوير كتلة MAC متعددة الأنماط ذات نقطة ثابتة جديدة تدعم ثلاثة أوضاع تشغيلية للتعامل بمرونة مع دقة إدخال مختلفة، مع تطبيق تقنية التوصيل الأنبوبي (pipelining) لتقليل التأخير بشكل أكبر. تظهر نتائج التركيب والمحاكاة على FPGA أن التصاميم المقترحة تحقق تخفيضات كبيرة في التأخير (حتى 75%) والمساحة (حتى 58%) مقارنة بالهياكل الحالية لوحدات MAC، مما يجعلها مناسبة لأنظمة معالجة الإشارات الرقمية عالية الأداء والتعلم العميق. [Extracted from the article]
Copyright of Iraqi Journal for Electrical & Electronic Engineering is the property of Republic of Iraq Ministry of Higher Education & Scientific Research (MOHESR) and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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Text:
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Header DbId: egs
DbLabel: Engineering Source
An: 192138991
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: Efficient Implementation of Fixed-Point MAC and Multimode MAC Blocks Based on Vedic Mathematic.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Hussein%2C+Fatima+Tariq%22">Hussein, Fatima Tariq</searchLink><relatesTo>1</relatesTo><i> pgs.fatima.tariq@uobasrah.edu.iq</i><br /><searchLink fieldCode="AR" term="%22AL-Assfor%2C+Fatemah+K%2E%22">AL-Assfor, Fatemah K.</searchLink><relatesTo>1</relatesTo>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Iraqi+Journal+for+Electrical+%26+Electronic+Engineering%22">Iraqi Journal for Electrical & Electronic Engineering</searchLink>. Dec2025, Vol. 21 Issue 2, p88-98. 11p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+signal+processing%22">Digital signal processing</searchLink><br /><searchLink fieldCode="DE" term="%22Mathematics%22">Mathematics</searchLink><br /><searchLink fieldCode="DE" term="%22Addition+%28Mathematics%29%22">Addition (Mathematics)</searchLink><br /><searchLink fieldCode="DE" term="%22Engineering+design%22">Engineering design</searchLink>
– Name: Abstract
  Label: Abstract (English)
  Group: Ab
  Data: Recently, the need for high speed multiply-accumulate (MAC) operations is crucial in numerous systems like 5G, deep learning, in addition to many digital signal processing (DSP) applications. This work offers an improved MAC (I-MAC) block of different bit-size based on Vedic Mathematic and employing a hybrid adder consists of an enhanced Brent-Kung with a carry-select adder (HBK-CSLA) to achieve the sum of products for the MAC. The work is then, developed to design a new multimode fixed-point (FX-Pt) MAC block by exploiting the proposed design of the I-MAC architecture. The proposed multimode MAC block supports three modes of operation; single 64-bit MAC operation, dual 32-bit multiplication with 32-bit single addition, and single 32-bit MAC operation. The design has utilized an adjusted architecture for the Vedic-multiplier (Adjusted-VM), a 64-bit HBK-CSLA, and a control circuit to select the desired mode of operation. The performance of the multi-mode MAC is then optimized by exploiting pipelining concept. The proposed architectures are synthesized in various FPGA families utilizing VHDL language in Xilinx ISE14.7 tool. The performance results have exposed that the proposed 64-bit I-MAC block have attained observable lessen 9.767% in delay and area usage of 47.49% compared with the most existing MAC block designs. [ABSTRACT FROM AUTHOR]
– Name: Abstract
  Label: Abstract (Arabic)
  Group: Ab
  Data: يركز المقال على تصميم وتنفيذ وحدات الضرب-التراكم (MAC) ذات النقطة الثابتة الفعالة وكتل MAC متعددة الأنماط المستندة إلى الرياضيات الفيدية (الرياضيات الفيدية) لتطبيقات معالجة الإشارات الرقمية (DSP) والتعلم العميق. يقدم المقال بنية محسنة لوحدة MAC (I-MAC) تستخدم مضاعف فيدي معدل (المضاعف الفيدي المعدل) مدمجًا مع جامع هجيني—وهو جامع برنت-كونغ المحسن وجامع اختيار الحمل (HBK-CSLA)—لتحسين السرعة واستخدام المساحة عبر عرضات بت مختلفة (8، 16، 32، و64 بت). بالإضافة إلى ذلك، تم تطوير كتلة MAC متعددة الأنماط ذات نقطة ثابتة جديدة تدعم ثلاثة أوضاع تشغيلية للتعامل بمرونة مع دقة إدخال مختلفة، مع تطبيق تقنية التوصيل الأنبوبي (pipelining) لتقليل التأخير بشكل أكبر. تظهر نتائج التركيب والمحاكاة على FPGA أن التصاميم المقترحة تحقق تخفيضات كبيرة في التأخير (حتى 75%) والمساحة (حتى 58%) مقارنة بالهياكل الحالية لوحدات MAC، مما يجعلها مناسبة لأنظمة معالجة الإشارات الرقمية عالية الأداء والتعلم العميق. [Extracted from the article]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Iraqi Journal for Electrical & Electronic Engineering is the property of Republic of Iraq Ministry of Higher Education & Scientific Research (MOHESR) and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.37917/ijeee.21.2.9
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 11
        StartPage: 88
    Subjects:
      – SubjectFull: Field programmable gate arrays
        Type: general
      – SubjectFull: Digital signal processing
        Type: general
      – SubjectFull: Mathematics
        Type: general
      – SubjectFull: Addition (Mathematics)
        Type: general
      – SubjectFull: Engineering design
        Type: general
    Titles:
      – TitleFull: Efficient Implementation of Fixed-Point MAC and Multimode MAC Blocks Based on Vedic Mathematic.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Hussein, Fatima Tariq
      – PersonEntity:
          Name:
            NameFull: AL-Assfor, Fatemah K.
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 12
              Text: Dec2025
              Type: published
              Y: 2025
          Identifiers:
            – Type: issn-print
              Value: 18145892
          Numbering:
            – Type: volume
              Value: 21
            – Type: issue
              Value: 2
          Titles:
            – TitleFull: Iraqi Journal for Electrical & Electronic Engineering
              Type: main
ResultId 1