APA (7th ed.) Citation

Vázquez, M., Tosini, M., & Leiva, L. (2026). Optimal Design of IEEE-754 Decimal Floating-Point Multipliers in FPGAs for DPD and BID Encoding. Circuits, Systems & Signal Processing, 45(4), 2825. https://doi.org/10.1007/s00034-025-03339-8

Chicago Style (17th ed.) Citation

Vázquez, Martín, Marcelo Tosini, and Lucas Leiva. "Optimal Design of IEEE-754 Decimal Floating-Point Multipliers in FPGAs for DPD and BID Encoding." Circuits, Systems & Signal Processing 45, no. 4 (2026): 2825. https://doi.org/10.1007/s00034-025-03339-8.

MLA (9th ed.) Citation

Vázquez, Martín, et al. "Optimal Design of IEEE-754 Decimal Floating-Point Multipliers in FPGAs for DPD and BID Encoding." Circuits, Systems & Signal Processing, vol. 45, no. 4, 2026, p. 2825, https://doi.org/10.1007/s00034-025-03339-8.