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Optimal Design of IEEE-754 Decimal Floating-Point Multipliers in FPGAs for DPD and BID Encoding.

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Title: Optimal Design of IEEE-754 Decimal Floating-Point Multipliers in FPGAs for DPD and BID Encoding.
Authors: Vázquez, Martín1,2 (AUTHOR) mvazquez@labset.exa.unicen.edu.ar, Tosini, Marcelo1,2 (AUTHOR) mtosini@labset.exa.unicen.edu.ar, Leiva, Lucas1,2 (AUTHOR) lleiva@labset.exa.unicen.edu.ar
Source: Circuits, Systems & Signal Processing. Apr2026, Vol. 45 Issue 4, p2825-2845. 21p.
Subjects: Field programmable gate arrays, Floating-point arithmetic, Mathematical optimization, Number systems, Programmable logic devices
Abstract: This paper presents efficient implementations of decimal floating-point (DFP) multipliers using Densely Packed Decimal (DPD) and Binary Integer Digit (BID) encoding on FPGA devices. The designs employ innovative techniques to optimize the use of dedicated resources in programmable hardware. Implementations were performed in Xilinx UltraScale+. For the DPD multiplier, they have computation times of 6.5 ns for Decimal32, 7.5 ns for Decimal64, and 9.2 ns for Decimal128. As for the BID multiplier, the computation time obtained is 9 ns for Decimal32, 13.2 ns for Decimal64, and 15.3 ns for Decimal128. The proposed architecture achieves better computation times than related works. Compared to previous architectures, the proposed DPD implementation achieves 1.19 speedup and 39% better LUT occupancy. Additionally, no studies are available for comparison with the proposed BID multiplier implementations.oxy_aqreply_start aqreply="We confirm that the corresponding author affiliation is correctly identified" [ABSTRACT FROM AUTHOR]
Copyright of Circuits, Systems & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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DbLabel: Engineering Source
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  Data: Optimal Design of IEEE-754 Decimal Floating-Point Multipliers in FPGAs for DPD and BID Encoding.
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  Data: <searchLink fieldCode="JN" term="%22Circuits%2C+Systems+%26+Signal+Processing%22">Circuits, Systems & Signal Processing</searchLink>. Apr2026, Vol. 45 Issue 4, p2825-2845. 21p.
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  Data: <searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Floating-point+arithmetic%22">Floating-point arithmetic</searchLink><br /><searchLink fieldCode="DE" term="%22Mathematical+optimization%22">Mathematical optimization</searchLink><br /><searchLink fieldCode="DE" term="%22Number+systems%22">Number systems</searchLink><br /><searchLink fieldCode="DE" term="%22Programmable+logic+devices%22">Programmable logic devices</searchLink>
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  Data: This paper presents efficient implementations of decimal floating-point (DFP) multipliers using Densely Packed Decimal (DPD) and Binary Integer Digit (BID) encoding on FPGA devices. The designs employ innovative techniques to optimize the use of dedicated resources in programmable hardware. Implementations were performed in Xilinx UltraScale+. For the DPD multiplier, they have computation times of 6.5 ns for Decimal32, 7.5 ns for Decimal64, and 9.2 ns for Decimal128. As for the BID multiplier, the computation time obtained is 9 ns for Decimal32, 13.2 ns for Decimal64, and 15.3 ns for Decimal128. The proposed architecture achieves better computation times than related works. Compared to previous architectures, the proposed DPD implementation achieves 1.19 speedup and 39% better LUT occupancy. Additionally, no studies are available for comparison with the proposed BID multiplier implementations.oxy_aqreply_start aqreply="We confirm that the corresponding author affiliation is correctly identified" [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of Circuits, Systems & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1007/s00034-025-03339-8
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      – Code: eng
        Text: English
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        PageCount: 21
        StartPage: 2825
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      – SubjectFull: Field programmable gate arrays
        Type: general
      – SubjectFull: Floating-point arithmetic
        Type: general
      – SubjectFull: Mathematical optimization
        Type: general
      – SubjectFull: Number systems
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      – SubjectFull: Programmable logic devices
        Type: general
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      – TitleFull: Optimal Design of IEEE-754 Decimal Floating-Point Multipliers in FPGAs for DPD and BID Encoding.
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            – D: 01
              M: 04
              Text: Apr2026
              Type: published
              Y: 2026
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