Optimal Design of IEEE-754 Decimal Floating-Point Multipliers in FPGAs for DPD and BID Encoding.
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| Title: | Optimal Design of IEEE-754 Decimal Floating-Point Multipliers in FPGAs for DPD and BID Encoding. |
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| Authors: | Vázquez, Martín1,2 (AUTHOR) mvazquez@labset.exa.unicen.edu.ar, Tosini, Marcelo1,2 (AUTHOR) mtosini@labset.exa.unicen.edu.ar, Leiva, Lucas1,2 (AUTHOR) lleiva@labset.exa.unicen.edu.ar |
| Source: | Circuits, Systems & Signal Processing. Apr2026, Vol. 45 Issue 4, p2825-2845. 21p. |
| Subjects: | Field programmable gate arrays, Floating-point arithmetic, Mathematical optimization, Number systems, Programmable logic devices |
| Abstract: | This paper presents efficient implementations of decimal floating-point (DFP) multipliers using Densely Packed Decimal (DPD) and Binary Integer Digit (BID) encoding on FPGA devices. The designs employ innovative techniques to optimize the use of dedicated resources in programmable hardware. Implementations were performed in Xilinx UltraScale+. For the DPD multiplier, they have computation times of 6.5 ns for Decimal32, 7.5 ns for Decimal64, and 9.2 ns for Decimal128. As for the BID multiplier, the computation time obtained is 9 ns for Decimal32, 13.2 ns for Decimal64, and 15.3 ns for Decimal128. The proposed architecture achieves better computation times than related works. Compared to previous architectures, the proposed DPD implementation achieves 1.19 speedup and 39% better LUT occupancy. Additionally, no studies are available for comparison with the proposed BID multiplier implementations.oxy_aqreply_start aqreply="We confirm that the corresponding author affiliation is correctly identified" [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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